Tms320C6211 Sdram Read - Texas Instruments TMS320C6201 Reference Manual

Tms320c6000 series peripherals

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SDRAM Interface

9.4.8.2 TMS320C6211/C6711 SDRAM Read

Figure 9–25. TMS320C6211 SDRAM Read

Figure 9–25 shows the 'C6211/C6711 performing a three word read burst from

SDRAM. The 'C6211/C6711 uses a burst length of four, and has a program-

mable CAS latency of either two or three cycles. The CAS latency is three cycles

in this example (CASL = 1). Since the default burst length is four words, the

SDRAM returns four pieces of data for every read command. If no additional ac-

cess are pending to the EMIF, as in Figure 9–25, the read burst completes and

the unneeded data is disregarded. If accesses are pending, the read burst can

be interrupted with a new command (READ,WRT,DEAC,DCAB), controlled by

the SDRAM extension register. If a new access is not pending, the DCAB/DEAC

command is not performed until the page information becomes invalid.

CAS latency = 3

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