Logical Mapping Of Cache Address - Texas Instruments TMS320C6201 Reference Manual

2.2.2.1 Cache Usage of CPU Address
Figure 2–2. Logical Mapping of Cache Address
31
Outside external range.
assumed to be 0
2.2.2.2 Cache Flush
2.2.2.3 Frame Replacement
Figure 2–2 shows how the cache uses the fetch packet address from the CPU:
5-bit fetch packet alignment: The five LSBs of the address are assumed to
be 0 because all program fetch requests are aligned on fetch packet
boundaries (eight words or 32 bytes).
11-bit tag block offset: Because the cache is directly mapped, any external
address maps to only one of the 2K frames. Any two fetch packets that are
separated by an integer multiple of 64K bytes map to the same frame.
Thus, bits 15–5 of the CPU address create the 11-bit block offset that de-
termines which of the 2K frames any particular fetch packet maps to.
10-bit tag: The cache assumes a maximum external address space of
64M bytes (from 0000 0000h–03FF FFFFh). Thus, bits 25–16 of the ad-
dress correspond to the tag that determines the original location of the
fetch packet in external memory space. The cache also has a separate
2K 11 tag RAM that holds all the tags. Each address location in this RAM
contains a 10-bit tag plus a valid bit that is used to record frame validity
information.
26 25 16 15
Tag
A dedicated valid bit in each address location of the tag RAM indicates whether
the contents of the corresponding cache frame is valid data. During a cache
flush, all of the valid bits are cleared to indicate that no cache frames have valid
data. Cache flushes occur only at the transition of the internal program
memory from mapped mode to cache enabled mode. You initiate this transition
by setting the cache enable pattern in the PCC field of the CPU control and
status register.
A cache miss is detected when the tag corresponding to the block offset of
the fetch packet address requested by the CPU does not correspond to bits
25–16 of the fetch packet address or if the valid bit at the block offset location
is clear. If enabled, the cache loads the fetch packet into the corresponding
frame, sets the valid bit, sets the tag to bits 25–16 of the requested address,
and delivers this fetch packet to the CPU after all eight instructions are
available.
TMS320C6201/C6701 Program and Data Memory
5 4
Fetch packet alignment.
Block offset
Internal Program Memory
0
assumed 0
2-5