DMA Registers
Table 5–1. DMA Control Registers by Address
5-6
Hex Byte
Address
0184 0000
0184 0004
0184 0008
0184 000C
0184 0010
0184 0014
0184 0018
0184 001C
0184 0020
0184 0024
0184 0028
0184 002C
0184 0030
0184 0034
0184 0038
0184 003C
0184 0040
0184 0044
0184 0048
0184 004C
0184 0050
0184 0054
0184 0058
0184 005C
0184 0060
0184 0064
0184 0068
0184 006C
0184 0070
Name
DMA channel 0 primary control
DMA channel 2 primary control
DMA channel 0 secondary control
DMA channel 2 secondary control
DMA channel 0 source address
DMA channel 2 source address
DMA channel 0 destination address
DMA channel 2 destination address
DMA channel 0 transfer counter
DMA channel 2 transfer counter
DMA global count reload register A
DMA global count reload register B
DMA global index register A
DMA global index register B
DMA global address register A
DMA global address register B
DMA channel 1 primary control
DMA channel 3 primary control
DMA channel 1 secondary control
DMA channel 3 secondary control
DMA channel 1 source address
DMA channel 3 source address
DMA channel 1 destination address
DMA channel 3 destination address
DMA channel 1 transfer counter
DMA channel 3 transfer counter
DMA global address register C
DMA global address register D
DMA auxiliary control register
Described
in Section
5.2.1
5.2.1
5.10
5.10
5.7
5.7
5.7
5.7
5.5
5.5
5.5
5.5
5.7.2
5.7.2
5.8
5.8
5.2.1
5.2.1
5.10
5.10
5.7
5.7
5.7
5.7
5.5
5.5
5.8
5.8
5.9.1