Hpic Register; Hpi Control Register (Hpic) Bit Descriptions - Texas Instruments TMS320C6201 Reference Manual

Figure 7–10. HPIC Register
31
rsvd
HR,CR,+0
15
rsvd
HR,CR,+0
Table 7–6. HPI Control Register (HPIC) Bit Descriptions
Bit Description
HWOB Halfword ordering bit
If HWOB = 1, the first halfword is least significant. If HWOB = 0, the first halfword
is most significant. HWOB affects both data and address transfers. Only the host
can modify this bit. HWOB must be initialized before the first data or address reg-
ister access.
DSPINT The host processor-to-CPU/DMA interrupt
HINT DSP-to-host interrupt. The inverted value of this bit determines the state of the
CPU HINT output.
HRDY Ready signal to host. Not masked by HCS (as the HRDY pin is).
If HRDY = 0, the internal bus is waiting for an HPI data access request to finish.
FETCH Host fetch request
The value read by the host or CPU from this register field is always 0.
The host writes a 1 to this bit to request a fetch into HPID of the word at the
address pointed to by HPIA. The 1 is never actually written to this bit, however.
7.3.2 Software Handshaking Using HRDY and FETCH
21 20
HRW,CR,+0
5 4
FETCH
HRW,CR,+0
As described previously, the HRDY pin can indicate to a host that an HPID
access has not finished. For example, the current HPID access can be waiting
for a previous HPID access write to finish or for a previous HPID prefetched read
to finish. Also, the current HPID read access can be waiting for its requested
data to arrive. The HRDY and FETCH bits in the HPIC register allow for a soft-
ware handshake that allows an HPI connection in systems in which a hardware
ready control is not desired. The FETCH and HRDY bits can be used to perform
a read transfer as follows:
19 18
HRDY HINT
HR,CR,+0 HRW,CR,+0 HRW,CR,+0 HRW,CR,+0
3 2
HRDY HINT
HR,CR,+1 HRW,CRW,+0 HRW,CRW,+0 HRW,CR,+0
HPI Registers
17
DSPINT HWOB
1
DSPINT HWOB
Section
7.4
7.3.3
7.3.4
7.3.2
7.3.2
Host-Port Interface
16
0
7-17