Texas Instruments TMS320C3x User Manual

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TMS320C3x

User's Guide

Literature Number: SPRU031E

2558539-9761 revision L

July 1997

Printed on Recycled Paper

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Summary of Contents for Texas Instruments TMS320C3x

Page 1 TMS320C3x User’s Guide Literature Number: SPRU031E 2558539-9761 revision L July 1997 Printed on Recycled Paper...
Page 2 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.
Page 3: Read This First
About This Manual This user’s guide serves as an applications reference book for the TMS320C3x generation of digital signal processors (DSPs). These include the TMS320C30, TMS320C31, TMS320LC31, and TMS320C32. Throughout the book, all refer- ences to ’C3x refer collectively to the ’C30, ’C31, ’LC31 and ’C32.
Page 4 Notational Conventions In syntax descriptions, the instruction, command, or directive is in bold typeface and parameters are in an italic typeface . Portions of a syntax that are in bold must be entered as shown; portions of a syntax that are in italics describe the type of information that must be entered.
Page 5 When ordering, please identify the book by its SPRU194) provides information to assist you in application development for the TMS320C3x generation of digital signal processors (DSPs). It includes example code and hardware connections for various appliances. It also defines the principles involved in many applications and gives the corresponding assembly language code for instructional purposes and for immediate use.
Page 6 Related Documentation from Texas Instruments / References TMS320C3x C Source Debugger User’s Guide (literature number TMS320 DSP Development Support Reference Guide (literature number TMS320 Third-Party Support Reference Guide (literature number References The publications in the following reference list contain useful information regarding functions, operations, and applications of digital signal processing (DSP).
Page 7 References Digital Signal Processing Applications with the TMS320 Family, Vol. III. Texas Instruments, 1990; Prentice-Hall, Inc., 1990. Gold, Bernard, and Rader, C.M. , Digital Processing of Signals. New York, NY: McGraw-Hill Company, Inc., 1969. Hamming, R.W., Digital Filters . Englewood Cliffs, NJ: Prentice-Hall, Inc., 1977.
Page 8 References Parsons, Thomas., Voice and Speech Processing. New York, NY: McGraw Hill Company, Inc., 1987. Rabiner, Lawrence R., and Schafer, R.W., Digital Processing of Speech Signals. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978. Shaughnessy, Douglas., Speech Communication. Reading, MA: Addison- Wesley, 1987. Image Processing Andrews, H.C., and Hunt, B.R., Digital Image Restoration .
Page 9 References Array Signal Processing Haykin, S., Justice, J.H., Owsley, N.L., Yen, J.L., and Kak, A.C. Array Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985. Hudson, J.E. Adaptive Array Principles. New York, NY: John Wiley and Sons, 1981. Monzingo, R.A., and Miller, J.W. Introduction to Adaptive Arrays. New York, NY: John Wiley and Sons, 1980.
Page 10 If You Need Assistance If You Need Assistance . . . World-Wide Web Sites TI Online Semiconductor Product Information Center (PIC) DSP Solutions 320 Hotline On-line Microcontroller Home Page Networking Home Page North America, South America, Central America Product Information Center (PIC) TI Literature Response Center U.S.A.
Page 11 When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated Technical Documentation Services, MS 702 P.O.
Page 12: Table Of Contents
..............A general description of the TMS320C30, TMS320C31, and TMS320C32, their key features, and typical applications. TMS320C3x Devices 1.1.1 TMS320C3x Key Specifications 1.1.2 TMS320C30 1.1.3 TMS320C31 and TMS320LC31 1.1.4...
Page 13 Contents CPU Registers ..............Description of the registers in the CPU register file.
Page 14 5.3.3 Single-Precision Floating-Point Format 5.3.4 Extended-Precision Floating-Point Format 5.3.5 Determining the Decimal Equivalent of a TMS320C3x Floating-Point Format 5.3.6 Conversion Between Floating-Point Formats Floating-Point Conversion (IEEE Std. 754) 5.4.1 Converting IEEE Format to 2s-Complement TMS320C3x Floating-Point Format 5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format...
Page 15 ............. . . Discussion of the pipeline of operations on the TMS320C3x...
Page 16 TMS320C30 and TMS320C31 External-Memory Interface Description of primary and expansion interfaces for the ’C30 and ’C31; external interface timing diagrams; programmable wait-states and bank switching. Overview ..............Memory Interface Signals 9.2.1 TMS320C30 Memory Interface Signals...
Page 17 12.2.12 Serial-Port Functional Operation 12.2.13 Serial-Port Initialization/Reconfiguration 12.2.14 TMS320C3x Serial-Port Interface Examples 12.3 DMA Controller ............
Page 18 ............. List of the opcode fields for the TMS320C3x instructions.
Page 19 Figures 1–1 TMS320C3x Devices Block Diagram 2–1 TMS320C30 Block Diagram 2–2 TMS320C31 Block Diagram 2–3 TMS320C32 Block Diagram 2–4 Central Processing Unit (CPU) 2–5 Memory Organization of the TMS320C30 2–6 Memory Organization of the TMS320C31 2–7 Memory Organization of the TMS320C32 2–8...
Page 20 Floating-Point Format 5–13 Converting from Extended-Precision Floating-Point Format to Single-Precision Floating-Point Format 5–14 IEEE Single-Precision Std. 754 Floating-Point Format 5–15 TMS320C3x Single-Precision 2s-Complement Floating-Point Format 5–16 Flowchart for Floating-Point Multiplication 5–17 Flowchart for Floating-Point Addition 5–18 Flowchart for NORM Instruction Operation 5–19...
Page 21 ............7–14 MAXSPEED Timing 8–1 TMS320C3x Pipeline Structure 8–2 Minor Clock Periods 8–3 2-Operand Instruction Word 8–4...
Page 22 10–5 STRB1 Control Register 10–6 IOSTRB Control Register 10–7 STRB Configuration 10–8 BNKCMP Example ............10–9 Bank-Switching Example 10–10 TMS320C32 External Memory Interface for 32-Bit SRAMs...
Page 23 12–30 Variable Burst Mode 12–31 Variable Standard Mode With Back-to-Back Frame Syncs 12–32 Variable Continuous Mode Without Frame Sync 12–33 TMS320C3x Zero-Glue-Logic Interface to TLC320C4x Example 12–34 DMA Basic Operation 12–35 Memory-Mapped Locations for DMA Channels 12–36 TMS320C30 and TMS320C31 DMA Global-Control Register 12–37 TMS320C32 DMA0 Global-Control Register...
Page 24 12–41 TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register 12–42 TMS320C32 CPU/DMA Interrupt-Enable Register 12–43 Mechanism for No DMA Synchronization 12–44 Mechanism for DMA Source Synchronization 12–45 Mechanism for DMA Destination Synchronization 12–46 Mechanism for DMA Source and Destination Synchronization 12–47 DMA Timing When Destination is On Chip 12–48 DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus 12–49 DMA Timing When Destination is an IOSTRB Bus 13–1...
Page 25 Index Steps and Bit-Reversed Addressing 7–1 Repeat-Mode Registers 7–2 Interlocked Operations 7–3 TMS320C3x Pin Operation at Reset 7–4 Reset, Interrupt, and Trap-Vector Locations for the TMS320C30/TMS320C31 Microprocessor Mode 7–5 Reset, Interrupt, and Trap-Branch Locations for the TMS320C31 Microcomputer Boot Mode 7–6...
Page 26 A–1 TMS320C3x Instruction Opcodes ............
Page 27 ............5–4 IEEE-to-TMS320C3x Conversion (Fast Version) 5–5 IEEE-to-TMS320C3x Conversion (Complete Version) 5–6...
Page 28 7–9 Multiprocessor Counter Manipulation 7–10 Implementation of V(S) 7–11 Implementation of P(S) 7–12 Code to Synchronize Two TMS320C3x Devices at the Software Level 7–13 Pipeline Delay of XF Pin Configuration 7–14 Incorrect Use of Interlocked Instructions 7–15 Pending Interrupt ............
Page 29 12–5 Serial-Port Register Setup #2 12–6 CPU Transfer With Serial Port Transmit Polling Method 12–7 TMS320C3x Zero-Glue-Logic Interface to Burr Brown A/D and D/A 12–8 Array Initialization With DMA 12–9 DMA Transfer With Serial-Port Receive Interrupt 12–10 DMA Transfer With Serial-Port Transmit Interrupt .
Page 30: Introduction
The TMS320C3x generation of digital signal processors (DSPs) are high- performance CMOS 32-bit floating-point devices in the TMS320 family of single-chip DSPs. The ’C3x generation integrates both system control and math-intensive functions on a single controller. This system integration allows fast, easy data movement and high-speed numeric processing performance.
Page 31: Tms320C3X Devices
TMS320C3x Devices 1.1 TMS320C3x Devices The ’C3x family consists of three members: the ’C30, ’C31, and ’C32. The ’C30, ’C31, and ’C32 can perform parallel multiply and arithmetic logic unit (ALU) operations on integer or floating-point data in a single cycle.
Page 32: Tms320C3X Key Specifications
Figure 1–1. TMS320C3x Devices Block Diagram Program cache (64 x 32) Expansion port (’C30) memory interface 32-bit IOSTRB data access XRDY 32-bit XD31-0 program access XA12-0 MSTRB RESET INT3-3 IACK XF1-0 MCBL/MP X2/CLKIN V DD V SS SHZE- MU6-0 1.1.1 TMS320C3x Key Specifications The key specifications of the ’C3x devices include the following:...
Page 33: Tms320C32
TMS320C3x Devices 1.1.4 TMS320C32 The ’C32 is the newest member of the ’C3x generation. They are enhanced versions of the ’C3x family and the lowest cost floating-point processors on the market today. These enhancements include a variable-width memory inter- face, two-channel DMA coprocessor with configurable priorities, flexible boot...
Page 34: Tms320C30, Tms320C31, Tms320Lc31, And Tms320C32 Comparison
Table 1–1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison Memory (words) On-Chip Cycle Cycle Device Freq Time Name (MHz) (ns) ’C30 (5 V) Boot loader Boot loader ’C31 Boot loader (5 V) Boot loader Boot loader Boot loader ’LC31 Boot loader (3.3 V) Off-Chip Peripherals...
Page 35 Table 1–1. TMS320C30, TMS320C31, TMS320LC31, and TMS320C32 Comparison (Continued) Memory (words) On-Chip Cycle Cycle Device Freq Time Name (MHz) (ns) Boot loader ’C32 Boot loader (5 V) Boot loader Off-Chip Peripherals Channels Cache Parallel Serial Timers 32/16/8 32/16/8 32/16/8 Package Type Temperature 144 PQFP...
Page 36: Typical Applications
1.2 Typical Applications The TMS320 family’s versatility, realtime performance, and multiple functions offer flexible design approaches in a variety of applications, which are shown in Table 1–2. Table 1–2. Typical Applications of the TMS320 Family General-Purpose DSP Digital filtering Convolution Correlation Hilbert transforms Fast Fourier transforms...
Page 37: Architectural Overview
Architectural Overview This chapter provides an architectural overview of the ’C3x processor. It includes a discussion of the CPU, memory interface, boot loader, peripherals, and direct memory access (DMA) of the ’C3x processor. Topic Overview ........... . . Central Processing Unit (CPU) CPU Primary Register File Other Registers...
Page 38: Overview
Overview 2.1 Overview The ’C3x architecture responds to system demands that are based on sophisti- cated arithmetic algorithms that emphasize both hardware and software solu- tions. High performance is achieved through the precision and wide dynamic range of the floating-point units, large on-chip memory, a high degree of parallel- ism, and the DMA controller.
Page 39: Tms320C30 Block Diagram
Figure 2–1. TMS320C30 Block Diagram Cache PDATA bus PADDR bus HOLD DDATA bus HOLDA DADDR1 bus STRB DADDR2 bus D31–D0 A23–A0 DMADATA bus DMAADDR bus Multiplexer RESET INT3–0 IACK MC/MP XF(1,0) V DD (3-0) IODV DD (1,0) ADV DD (1,0) PDV DD DDV DD (1,0) MDV DD...
Page 40: Tms320C31 Block Diagram
Overview Figure 2–2. TMS320C31 Block Diagram Cache PDATA bus PADDR bus HOLD DDATA bus HOLDA DADDR1 bus STRB R / W DADDR2 bus D31– D0 A23 – A0 DMADATA bus DMAADDR bus Multiplexer RESET INT(3 – 0) IACK MCBL / MP XF(1,0) (19 –...
Page 41: Tms320C32 Block Diagram
Figure 2–3. TMS320C32 Block Diagram Program cache 32 24 PDATA bus PADDR bus DDATA bus RESET DADDR1 bus INT(3-0) IACK DADDR2 bus XF(1,0) DMADATA bus DMAADDR bus MCBL / MP CLKIN (6-0) (6-0) (3-9) (11-3) (7-0) (5-0) Multiplexer SUBS EMU0–3 Legend: PDATA bus –...
Page 42: Central Processing Unit (Cpu)
Central Processing Unit (CPU) 2.2 Central Processing Unit (CPU) The ’C3x devices (’C30, ’C31, and ’C32) have a register-based CPU architec- ture. The CPU consists of the following components: Floating-point/integer multiplier Arithmetic logic unit (ALU) 32-bit barrel shifter Internal buses (CPU1/CPU2 and REG1/REG2) Auxiliary register arithmetic units (ARAUs) CPU register file Figure 2–4 shows a diagram of the various CPU components.
Page 43: Central Processing Unit (Cpu)
Figure 2–4. Central Processing Unit (CPU) † Disp = an 8-bit integer displacement carried in a program-control instruction DADDR1 bus DADDR2 bus DDATA bus Multiplexer ARAU0 Central Processing Unit (CPU) CPU1 bus CPU2 bus REG1 bus REG2 bus 32-bit barrel Multiplier shifter Extended-...
Page 44: Floating-Point/Integer Multiplier
Central Processing Unit (CPU) 2.2.1 Floating-Point/Integer Multiplier The multiplier performs single-cycle multiplications on 24-bit integer and 32-bit floating-point values. The ’C3x implementation of floating-point arithmetic allows for floating-point or fixed-point operations at speeds up to 33-ns per instruction cycle. To gain even higher throughput, you can use parallel instructions to perform a multiply and an ALU operation in a single cycle.
Page 45: Cpu Primary Register File
2.3 CPU Primary Register File The ’C3x provides 28 registers in a multiport register file that is tightly coupled to the CPU. Table 2–1 lists the register names and functions. All of the primary registers can be operated upon by the multiplier and ALU and can be used as general-purpose registers.
Page 46 CPU Primary Register File Table 2–1. Primary CPU Registers (Continued) Register Name The extended-precision registers (R7–R0) can store and support operations on 32-bit integers and 40-bit floating-point numbers. Any instruction that assumes the operands are floating-point numbers uses bits 39–0. If the operands are either signed or unsigned integers, only bits 31–0 are used;...
Page 47 CPU Primary Register File The ARAU uses the 32-bit block size register (BK) in circular addressing to specify the data block size. The system-stack pointer (SP) is a 32-bit register that contains the address of the top of the system stack. The SP always points to the last element pushed onto the stack.
Page 48: Other Registers
Other Registers 2.4 Other Registers The program-counter (PC) is a 32-bit register containing the address of the next instruction to fetch. Although the PC is not part of the CPU register file, it is a register that can be modified by instructions that modify the program flow. The instruction register (IR) is a 32-bit register that holds the instruction opcode during the decode phase of the instruction.
Page 49: Memory Organization
2.5 Memory Organization The total memory space of the ’C3x is 16M (million) 32-bit words. Program, data, and I/O space are contained within this 16M-word address space, allowing the storage of tables, coefficients, program code, or data in either RAM or ROM.
Page 50: Memory Organization Of The Tms320C30
Memory Organization Figure 2–5. Memory Organization of the TMS320C30 Cache (64 32) PDATA bus PADDR bus HOLD DDATA bus HOLDA DADDR1 bus STRB DADDR2 bus D31–D0 A23–A0 DMADATA bus DMAADDR bus Program counter/ instruction register 2-14 É É É É É É...
Page 51: Memory Organization Of The Tms320C31
Figure 2–6. Memory Organization of the TMS320C31 Cache PDATA bus PADDR bus HOLD DDATA bus HOLDA DADDR1 bus STRB DADDR2 bus D31–D0 A23–A0 DMADATA bus DMAADDR bus Program counter/ instruction register block 0 block 1 Memory Organization É É É É É...
Page 52: Memory Organization Of The Tms320C32
Memory Organization Figure 2–7. Memory Organization of the TMS320C32 A23 – A0 D31 – D0 HOLD HOLDA PRGW Enhanced STRB0_B3/A-1 external STRB0_B2/A-2 memory STRB0_B1 interface STRB0_B0 STRB1_B3/A-1 STRB1_B2/A-2 STRB1_B1 STRB1_B0 IOSTRB A 64 of code, which greatly reduces the number of off-chip accesses. This allows for code to be stored off chip in slower, lower-cost memories.
Page 53: Memory Addressing Modes
2.5.2 Memory Addressing Modes The ’C3x supports a base set of general-purpose instructions as well as arithmetic- intensive instructions that are particularly suited for digital signal processing and other numeric-intensive applications. See Chapter 6, Addressing Modes , for more information. Four groups of addressing modes are provided on the ’C3x.
Page 54: Internal Bus Operation
Internal Bus Operation 2.6 Internal Bus Operation Much of the ’C3x’s high performance is due to internal busing and parallelism. Separate buses allow for parallel program fetches, data accesses, and DMA accesses: Program buses: PADDR and PDATA Data buses: DADDR1, DADDR2, and DDATA DMA buses: DMAADDR and DMADATA These buses connect all of the physical spaces (on-chip memory, off-chip memory, and on-chip peripherals) supported by the ’C3x.
Page 55: External Memory Interface
2.7 External Memory Interface The ’C30 provides two external interfaces: the primary bus and the expansion bus. The ’C31 provides one external interface: the primary bus. The ’C32 pro- vides one enhanced external interface with three independent multi-function strobes. These buses consist of a 32-bit data bus and a set of control signals. The primary and enhanced memory buses have a 24-bit address bus, whereas the expansion bus has a 13-bit address bus.
Page 56: Tms320C32 8-, 16-, And 32-Bit Data Memory
External Memory Interface 2.7.2 TMS320C32 8-, 16-, and 32-Bit Data Memory The ’C32 external memory interface can load and store 8-, 16-, or 32-bit quanti- ties into external memory and convert them into an internally-equivalent 32-bit representation. The external memory interface accomplishes this without changing the CPU instruction set.
Page 57: Interrupts
Interrupts 2.8 Interrupts The ’C3x supports four external interrupts (INT3–INT0), a number of internal interrupts, and a nonmaskable external RESET signal. These can be used to interrupt either the DMA or the CPU. When the CPU responds to the interrupt, the IACK pin can be used to signal an external interrupt acknowledge.
Page 58: Peripherals
Peripherals 2.9 Peripherals All ’C3x peripherals are controlled through memory-mapped registers on a dedi- cated peripheral bus. This peripheral bus is composed of a 32-bit data bus and a 24-bit address bus. This peripheral bus permits straightforward communica- tion to the peripherals. The ’C3x peripherals include two timers and two serial ports (only one serial port and one DMA coprocessor are available on the ’C31 and one serial port and two DMA coprocessor channels on the ’C32).
Page 59: Timers
2.9.1 Timers The two timer modules are general-purpose 32-bit timer/event counters with two signaling modes and internal or external clocking. They can signal internally to the ’C3x or externally to the outside world at specified intervals or they can count external events. Each timer has an I/O pin that can be used as an input clock to the timer, as an output signal driven by the timer, or as a general-purpose I/O pin.
Page 60: Direct Memory Access (Dma)
Direct Memory Access (DMA) 2.10 Direct Memory Access (DMA) The on-chip DMA controller can read from or write to any location in the memory map without interfering with the CPU operation. The ’C3x can inter- face to slow, external memories and peripherals without reducing throughput to the CPU.
Page 61: Dma Controller
Direct Memory Access (DMA) Figure 2–10. DMA Controller DMADATA bus DMAADDR bus DMA controller Global-control register Source-address register Destination-address register Transfer-counter register Architectural Overview 2-25...
Page 62: Tms320C30, Tms320C31, And Tms320C32 Differences
TMS320C30, TMS320C31, and TMS320C32 Differences 2.11 TMS320C30, TMS320C31, and TMS320C32 Differences Table 2–2 shows the major differences between the ’C32, ’C31, and the ’C30 devices. 2-26...
Page 63: Feature Set Comparison
Table 2–2. Feature Set Comparison Feature ’C30 External bus Two buses: Primary bus: 32-bit data 24-bit address STRB active for 0h–7FFFFFh and 80A000h–FFFFFFh Expansion bus: 32-bit data 13-bit address MSTRB active for 800000h–801FFFh IOSTRB active for 804000h–805FFFh Boot loader On-chip RAM address: 809800h–809FFFh 1 channel...
Page 64: Cpu Registers
The central processing unit (CPU) register file contains 28 registers that can be operated on by the multiplier and arithmetic logic unit (ALU). Included in the register file are the auxiliary registers, extended-precision registers, and index registers. Three registers in the ’C32 CPU register file have been modified to support new features (2-channel DMAs, program execution from 16-bit memory width, etc.) The registers modified in the ’C32 are: the status (ST) register, interrupt-enable (IE) register, and interrupt flag (IF) register.
Page 65: Cpu Multiport Register File
CPU Multiport Register File 3.1 CPU Multiport Register File The ’C3x provides 28 registers in a multiport register file that is tightly coupled to the CPU. The program counter (PC) is not included in the 28 registers. All of these registers can be operated on by the multiplier and the ALU and can be used as general-purpose 32-bit registers.
Page 66: Extended-Precision Register Floating-Point Format
The registers also have some special functions for which they are particularly appropriate. For example, the eight extended-precision registers are especially suited for maintaining extended-precision floating-point results. The eight auxiliary registers support a variety of indirect addressing modes and can be used as general-purpose 32-bit integer and logical registers.
Page 67 CPU Multiport Register File 3.1.2 Auxiliary Registers (AR7–AR0) The CPU can access the eight 32-bit auxiliary registers (AR7–AR0), and the two auxiliary register arithmetic units (ARAUs) can modify them. The primary function of the auxiliary registers is the generation of 24-bit addresses. However, they can also operate as loop counters in indirect addressing or as 32-bit general- purpose registers that can be modified by the multiplier and ALU.
Page 68: Status Register (Tms320C30 Andtms320C31)
3.1.7 Status (ST) Register The status (ST) register contains global information about the state of the CPU. Operations usually set the condition flags of the status register according to whether the result is 0, negative, etc. This includes register load and store operations as well as arithmetic and logical functions.
Page 69: Status Register Bits
CPU Multiport Register File Table 3–2. Status Register Bits Bit Name Reset Value Name Note: If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset. Description Carry flag Carry condition flag Overflow flag Overflow condition flag Zero flag...
Page 70 Table 3–2. Status Register Bits (Continued) Bit Name Reset Value Name Cache freeze Cache clear Global interrupt-enable INT config Interrupt configuration (‘C32 only) Note: If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset. CPU Multiport Register File Description Enables or disables the instruction cache...
Page 71 CPU Multiport Register File Table 3–2. Status Register Bits (Continued) Bit Name Reset Value PRGW Dependent on PRGW pin level Note: If a load of the status register occurs simultaneously with a CPU interrupt pulse trying to reset GIE, GIE is reset. Name Description Program width status...
Page 72: Cpu/Dma Interrupt-Enable (Ie) Register (Tms320C30 And Tms320C31)
3.1.8 CPU/DMA Interrupt-Enable (IE) Register The CPU/DMA interrupt-enable (IE) register of the ’C30, ’C31, and ’C32 are 32-bit registers (see Figure 3–5 and Figure 3–6). The CPU interrupt-enable bits are in locations 10–0 for ’C30 and ’C31 devices, and 11–0 for ’C32 devices. The direct memory access (DMA) interrupt-enable bits are in locations 26–16 for ‘C30 and ‘C31 devices, and 31–16 for ’C32 devices.
Page 73: Ie Bits And Functions
CPU Multiport Register File Table 3–3. IE Bits and Functions Abbreviation EINT0 (CPU) EINT1 (CPU) EINT2 (CPU) EINT3 (CPU) EXINT0 (CPU) ERINT0 (CPU) EXINT1 (CPU) ERINT1 (CPU) ETINT0 (CPU) ETINT1 (CPU) EDINT (CPU) EDINT0 (CPU) EDINT1 (CPU) EINT0 (DMA) EINT1 (DMA) EINT2 (DMA) EINT3 (DMA) EINT0 (DMA0)
Page 74: Cpu Interrupt Flag (If) Register
Table 3–3. IE Bits and Functions(Continued) Abbreviation ETINT0 (DMA) ETINT1 (DMA) ETINT0 (DMA0) ETINT1 (DMA0) ETINT0 (DMA1) ETINT1 (DMA1) EDINT (DMA) EDINT1 (DMA0) EDINT0 (DMA1) EINT0 (DMA1) EINT1 (DMA1) EINT2 (DMA1) EINT3 (DMA1) 3.1.9 CPU Interrupt Flag (IF) Register Figure 3–7, Figure 3–8, and Figure 3–9 show the 32-bit CPU interrupt flag reg- isters (IF) for the ‘C30, ‘C31, and ‘C32 devices, respectively.
Page 75: Tms320C30 Cpu Interrupt Flag (If) Register
CPU Multiport Register File Figure 3–7. TMS320C30 CPU Interrupt Flag (IF) Register 31–16 15–12 DINT Notes: 1) xx = reserved bit, read as 0 2) yy = reserved bit, set to 0 at reset; can store value 3) R = read, W = write Figure 3–8.
Page 76: If Bits And Functions
Table 3–4. IF Bits and Functions Reset Function Name Value INT0 External interrupt 0 flag INT1 External interrupt 1 flag INT2 External interrupt 2 flag INT3 External interrupt 3 flag XINT0 Serial port 0 transmit flag RINT0 Serial port 0 receive flag XINT1 Serial port 1 transmit flag (‘C30 only) RINT1...
Page 77: Effective Base Address Of The Interrupt-Trap Vector Table
CPU Multiport Register File 3.1.9.1 Interrupt-Trap Table Pointer (ITTP) Similar to the rest of the ‘C3x device family, the ’C32’s reset vector location remains at address 0. However, the interrupt and trap vectors are relocatable. This is achieved by the interrupt-trap table pointer (ITTP) bit field in the CPU interrupt flag register, shown in Figure 3–9.
Page 78: Interrupt And Trap Vector Locations
Figure 3–11.Interrupt and Trap Vector Locations EA (ITTP) + 00h EA (ITTP) + 01h EA (ITTP) + 02h EA (ITTP) + 03h EA (ITTP) + 04h EA (ITTP) + 05h EA (ITTP) + 06h EA (ITTP) + 07h EA (ITTP) + 08h EA (ITTP) + 09h EA (ITTP) + 0Ah EA (ITTP) + 0Bh...
Page 79: I/O Flag (Iof) Register
CPU Multiport Register File 3.1.10 I/O Flag (IOF) Register The I/O flag (IOF) register is shown in Figure 3–12 and controls the function of the dedicated external pins, XF0 and XF1. These pins can be configured for input or output. The pins can also be read from and written to. At reset, 0 is written to this register.
Page 80 3.1.11 Repeat-Counter (RC) and Block-Repeat (RS, RE) Registers The repeat-counter (RC) register is a 32-bit register that specifies the number of times a block of code is to be repeated when a block repeat is performed. If RC contains the number n , the loop is executed n + 1 times. The 32-bit repeat start-address (RS) register contains the starting address of the program-memory block to be repeated when the CPU is operating in the repeat mode.
Page 81 Other Registers 3.2 Other Registers 3.2.1 Program-Counter (PC) Register The program counter (PC) is a 32-bit register containing the address of the next instruction fetch. While the program-counter register is not part of the CPU register file, it can be modified by instructions that modify the program flow.
Page 82: Reserved Bits And Compatibility
Reserved Bits and Compatibility 3.3 Reserved Bits and Compatibility To retain compatibility with future members of the ’C3x family of microprocessors, reserved bits that are read as 0 must be written as 0. You must not modify the current value of a reserved bit that has an undefined value. In other cases, you should maintain the reserved bits as specified.
Page 83 Memory and the Instruction Cache The ’C3x provides a total memory space of 16M (million) 32-bit words that contain program, data, and I/O space. Two RAM blocks of 1K on the ’C30 and ’C31) or two RAM blocks of 256 and a ROM block of 4K 32 bits (available only on the ’C30) or boot loader (available on the ’C31 and the ’C32) permit two CPU accesses in a single cycle.
Page 84 Memory 4.1 Memory The ’C3x accesses a total memory space of 16M (million) 32-bit words of pro- gram, data, and I/O space and allows tables, coefficients, program code, or data to be stored in either RAM or ROM. In this way, you can maximize memory usage and allocate memory space as desired.
Page 85 Microcomputer Mode In microcomputer mode, the 4K on-chip ROM is mapped into locations 0h–0FFFh. There are 192 locations (0h–0BFh) within this block for interrupt vectors, trap vectors, and a reserved space (’C30). Locations 1000h– 7FFFFFh are accessed over the external memory port (STRB active). Section 4.1.2, Peripheral Bus Memory Map , on page 4-9 describes the peripheral memory maps in greater detail and Section 4.2, Reset/Interrupt/Trap Vector Map , on page 4-14 provides the vector locations for reset, interrupts, and traps.
Page 86: Tms320C30 Memory Maps
Memory Figure 4–1. TMS320C30 Memory Maps Reset, interrupt, trap vectors, and reserved locations (64) (external STRB active) 03Fh 040h 7FFFFFh 800000h 801FFFh 802000h 803FFFh 804000h 805FFFh 806000h 807FFFh 808000h (6K words internal) 8097FFh 809800h (1K words internal) 809BFFh 809C00h (1K words internal) 809FFFh 80A000h FFFFFFh...
Page 87 4.1.1.2 TMS320C31 Memory Map The memory map depends on whether the processor is running in micropro- cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The memory maps for these modes are similar (see Figure 4–2 on page 4-6). Locations 800000h–807FFFh are reserved.
Page 88: Tms320C31 Memory Maps
Memory Figure 4–2. TMS320C31 Memory Maps Reset, interrupt, trap vectors, and reserved locations (64) (external STRB active) 03Fh 040h 7FFFFFh 800000h 807FFFh 808000h memory-mapped (6K words internal) 8097FFh 809800h (1K words internal) 809BFFh 809C00h (1K words internal) 809FFFh 80A000h FFFFFFh Microprocessor mode †...
Page 89 4.1.1.3 TMS320C32 Memory Map The memory map depends on whether the processor is running in micropro- cessor mode (MCBL/MP = 0) or microcomputer mode (MCBL/MP = 1). The memory maps for these modes are similar (see Figure 4–3 on page 4-8). Locations 800000h–807FFFh, 809800h–80FFFh, and 830000H–87FDFFh are reserved.
Page 90: Tms320C32 Memory Maps
Memory Figure 4–3. TMS320C32 Memory Maps Reset-vector location External memory STRB0 active (8.192M words) 7FFFFFh 800000h Reserved (32K words) 807FFFh 808000h Peripheral bus memory-mapped registers (6K words internal) 8097FFh 809800h Reserved (26K words) 80FFFFh 810000h External memory IOSTRB active (128K) (128K words) 82FFFFh 830000h...
Page 91 4.1.2 Peripheral Bus Memory Map The following sections describe the peripherial bus memory maps for the ’C30, ’C31, and ’C32. 4.1.2.1 TMS320C30 Peripheral Bus Memory Map The ’C30 memory-mapped peripheral registers are located starting at address 808000h. Figure 4–4 on page 4-10 shows the peripheral bus memory map. The shaded blocks are reserved.
Page 92: Tms320C30 Peripheral Bus Memory-Mapped Registers
Memory Figure 4–4. TMS320C30 Peripheral Bus Memory-Mapped Registers 4-10 808000h DMA global control 808004h DMA source address 808006h DMA destination address 808008h DMA transfer counter 808020h Timer 0 global control Timer 0 counter 808024h Timer 0 period 808028h Timer 1 global control 808030h Timer 1 counter 808034h...
Page 93: Tms320C31 Peripheral Bus Memory-Mapped Registers
4.1.2.2 TMS320C31 Peripheral Bus Memory Map The ’C31 memory-mapped peripheral registers are located starting at address 808000h. Figure 4–5 shows the peripheral bus memory map. The shaded blocks are reserved. Figure 4–5. TMS320C31 Peripheral Bus Memory-Mapped Registers 808000h DMA global control 808004h DMA source address 808006h...
Page 94 Memory 4.1.2.3 TMS320C32 Peripheral Bus Memory Map The ’C32’s memory-mapped peripheral and external-bus control registers are located starting at address 808000h, as shown in Figure 4–6 on page 4-13. The shaded blocks are reserved. 4-12...
Page 95: Tms320C32 Peripheral Bus Memory-Mapped Registers
Figure 4–6. TMS320C32 Peripheral Bus Memory-Mapped Registers 808000h 808004h 808006h 808008h 808010h 808014h 808016h 808018h 808020h 808024h 808028h 808030h 808034h 808038h 808040h 808042h 808043h 808044h 808045h 808046h 808048h 80804Ch 808060h 808064h 808068h 8097FFh DMA 0 global control DMA 0 source address DMA 0 destination address DMA 0 transfer counter DMA 1 global control...
Page 96: Reset/Interrupt/Trap Vector Map
Reset/Interrupt/Trap Vector Map 4.2 Reset/Interrupt/Trap Vector Map The addresses for the reset, interrupt, and trap vectors are 00h–3Fh, as shown in Figure 4–7 and Figure 4–8. The reset vector contains the address of the reset routine. ’C30 and ’C31 Microprocessor and Microcomputer Modes In the microprocessor mode of the ’C30 and ’C31 and the microcomputer mode of the ’C30, the reset interrupt and trap vectors stored in locations 0h–3Fh are the addresses of the starts of the respective reset, interrupt,...
Page 97: Reset, Interrupt, And Trap Vector Locations For The Tms320C30 Microprocessor Mode
Figure 4–7. Reset, Interrupt, and Trap Vector Locations for the TMS320C30 Microprocessor Mode Note: Traps 28–31 Traps 28–31 are reserved; do not use them. RESET INT0 INT1 INT2 INT3 XINT0 RINT0 XINT1 RINT1 TINT0 TINT1 DINT Reserved TRAP 0 TRAP 27 TRAP 28 (reserved) TRAP 29 (reserved) TRAP 30 (reserved)
Page 98: Reset, Interrupt, And Trap Vector Locations For Thetms320C31 Microprocessor Mode
Reset/Interrupt/Trap Vector Map Figure 4–8. Reset, Interrupt, and Trap Vector Locations for theTMS320C31 Microprocessor Mode Note: Traps 28–31 Traps 28–31 are reserved; do not use them. 4-16 RESET INT0 INT1 INT2 INT3 XINT0 RINT0 XINT1 (Reserved) RINT1 (Reserved) TINT0 TINT1 DINT Reserved TRAP 0...
Page 99: Interrupt And Trap Branch Instructions For The Tms320C31 Microcomputer Mode
Figure 4–9. Interrupt and Trap Branch Instructions for the TMS320C31 Microcomputer Mode Note: Traps 28–31 Traps 28–31 are reserved; do not use them. Unlike the ’C31’s microprocessor mode, the ’C31 microcomputer/boot loader mode uses a dual-vectoring scheme to service interrupts and trap requests. In this dual vectoring scheme, a branch instruction rather than a vector address is used.
Page 100: Interrupt And Trap Vector Locations For Tms320C32
Reset/Interrupt/Trap Vector Map Figure 4–10. Interrupt and Trap Vector Locations for TMS320C32 EA (ITTP) + 00h EA (ITTP) + 01h EA (ITTP) + 02h EA (ITTP) + 03h EA (ITTP) + 04h EA (ITTP) + 05h EA (ITTP) + 06h EA (ITTP) + 07h EA (ITTP) + 08h EA (ITTP) + 09h...
Page 101: Address Partitioning For Cache Control Algorithm
4.3 Instruction Cache A 64 32-bit instruction cache speeds instruction fetches and lowers system cost by caching program fetches from external memory. The instruction cache allows the use of slow, external memories while still achieving single-cycle access performances. This reduces the number of off-chip accesses necessary and allows code to be stored off-chip in slower, lower-cost memories.
Page 102: Instruction-Cache Architecture
Instruction Cache Figure 4–12. Instruction-Cache Architecture Segment start address registers flags SSA register 0 SSA register 1 The LRU stack determines which of the two segments qualifies as the least recently used after each access to the cache. Each time a segment is accessed, its segment number is removed from the LRU stack and pushed onto the top of the LRU stack.
Page 103 4.3.2 Instruction-Cache Algorithm When the ’C3x requests an instruction word from external memory, one of two possible actions occurs: a cache hit or a cache miss . Cache Hit. The cache contains the requested instruction, and the following actions occur: Cache Miss.
Page 104 Instruction Cache Only instructions may be fetched from the program cache. All reads and writes of data in memory bypass the cache. Program fetches from internal memory do not modify the cache and do not generate cache hits or misses. The pro- gram cache is a single-access memory block.
Page 105: Combined Effect Of The Ce And Cf Bits
Table 4–1. Combined Effect of the CE and CF Bits When the CE or CF bits of the CPU status register are modified, the following four instructions may or may not be fetched from the cache or external memory (see Example 4–1). When the CC bit of the CPU status register is modified, the following five instruc- tions may or may not be fetched from the cache before the cache is cleared (see Example 4–1).
Page 106 Data Formats and Floating-Point Operation In the ’C3x architecture, data is organized into three fundamental types: integer, unsigned integer, and floating-point. The terms integer and signed integer are equivalent. The ’C3x supports short and single-precision formats for signed and unsigned integers. It also supports short, single-precision, and extended- precision formats for floating-point data.
Page 107: Short-Integer Format And Sign-Extension Of Short Integers
Integer Formats 5.1 Integer Formats The ’C3x supports two integer formats: a 16-bit short-integer format and a 32-bit single-precision integer format. Note: When extended-precision registers are used as integer operands, only bits 31–0 are used; bits 39–32 remain unchanged. 5.1.1 Short-Integer Format The short-integer format is a 16-bit 2s-complement integer format for immediate- integer operands.
Page 108: Short Unsigned-Integer Format And Zero Fill
5.2 Unsigned-Integer Formats The ’C3x supports two unsigned-integer formats: a 16-bit short format and a 32-bit single-precision format. Note: In extended-precision registers, the unsigned-integer operands use only bits 31– 0; bits 39–32 remain unchanged. 5.2.1 Short Unsigned-Integer Format Figure 5–3 shows the16-bit, short, unsigned-integer format for immediate unsigned-integer operands.
Page 109: General Floating-Point Format
Floating-Point Formats 5.3 Floating-Point Formats The ’C3x supports four floating-point formats: A short floating-point format for immediate floating-point operands, consisting of a 4-bit exponent, a sign bit, and an 11-bit fraction (’C32 only) A short floating-point format for use with 16-bit floating-point data types, consisting of a 2s-complement, 8-bit exponent field, a sign bit, and a 7-bit fraction A single-precision floating-point format by an 8-bit exponent field, a sign...
Page 110: Short Floating-Point Format
The exponent field is a 2s-complement number that determines the factor of 2 by which the number is multiplied. Essentially, the exponent field shifts the binary point in the mantissa. If the exponent is positive, then the binary point is shifted to the right.
Page 111: Tms320C32 Short Floating-Point Format For External 16-Bit Data
Floating-Point Formats The following examples illustrate the range and precision of the short floating- point format: Most positive: Least positive: Least negative: x = (–1– 2 Most negative: 5.3.2 TMS320C32 Short Floating-Point Format for External 16-Bit Data To facilitate the handling of 16-bit floating-point data types, the ‘C32 uses a new short floating-point format for external 16-bit data types.
Page 112: Single-Precision Floating-Point Format
The following examples illustrate the range and precision of the ‘C32 short floating-point format for external 16-bit data: Most positive: Least positive Least negative: Most negative: Note that the floating-point instructions (such as LDF, MPYF, ADDF) and the integer instructions (such as LDI, MPYI, ADDI) produce different results when accessing the same memory location.
Page 113: Extended-Precision Floating-Point Format
Floating-Point Formats You must use the following reserved values to represent 0 in the single-precision floating-point format: e = – 128 s = 0 f = 0 The following examples illustrate the range and precision of the single-precision floating-point format: Most positive: Least positive: Least negative:...
Page 114: Determining The Decimal Equivalent Of A Tms320C3X
Least positive: Least negative: Most negative: 5.3.5 Determining the Decimal Equivalent of a TMS320C3x Floating-Point Format To convert a ‘C3x floating-point number to its decimal equivalent, follow these steps: Step 1: Convert the exponent field to its decimal representation. Step 2: Convert the mantissa field to its decimal representation.
Page 115 Floating-Point Formats Rewrite the mantissa as: Step 3: Shift the decimal point of the mantissa according to the value of the Example 5–1. Positive Number 0000 0010 0100 0000 0000 0000 0000 0000 Exponent = Sign Fraction = Value 5-10 Mantissa exponent.
Page 116 Example 5–2. Negative Number 0000 0001 1100 0000 0000 0000 0000 0000 Exponent = Sign Fraction = Value Example 5–3. Fractional Number 1111 1011 0100 0000 0000 0000 0000 0000 Exponent = Sign Fraction = Value 0000 0001 .10000 10.1 = 101 .
Page 117: Floating-Point Format
Floating-Point Formats 5.3.6 Conversion Between Floating-Point Formats Floating-point operations assume several different formats for inputs and out- puts. These formats often require conversion from one floating-point format to another (for example, short floating-point format to extended-precision floating- point format). Format conversions occur automatically in hardware, with no overhead, as a part of the floating-point operations.
Page 118: Converting From Single-Precision Floating-Point Format To Extended-Precision
Figure 5–12. Converting from Single-Precision Floating-Point Format to Extended-Precision Floating-Point Format The 8 LSBs of the mantissa field are filled with 0s. Figure 5–13. Converting from Extended-Precision Floating-Point Format to Single-Precision Floating-Point Format The 8 LSBs of the mantissa field are truncated. 24 23 22 Single-precision floating-point format Extended-precision floating-point format...
Page 119: Floating-Point Conversion (Ieee Std. 754)
Floating-Point Conversion (IEEE Std. 754) 5.4 Floating-Point Conversion (IEEE Std. 754) The ‘C3x floating-point format is not compatible with the IEEE standard 754 format. The IEEE floating-point format uses sign-magnitude notation for the mantissa, and the exponent is biased by 127. In a 32-bit word representing a floating-point number, the first bit is the sign bit.
Page 120: Converting Ieee Format To 2S-Complement Tms320C3X
For this representation, e is treated as a 2s-complement integer. The fraction and sign bit form a normalized 2s-complement mantissa. Note: Differentiating Symbols for IEEE and TMS320C3x Formats To differentiate between the symbols that define these two formats, all IEEE...
Page 121 Floating-Point Conversion (IEEE Std. 754) Case 1 maps the IEEE positive NaNs and positive infinity to the single-preci- sion 2s-complement most positive number. Overflow is also signaled to allow you to check for these special cases. Case 2 maps the IEEE negative NaNs and negative infinity to the single- precision 2s-complement most negative number.
Page 122 Keith Henry of Apollo Computer, Inc. The other routines were based on this initial input. Example 5–4. IEEE-to-TMS320C3x Conversion (Fast Version) TITLE IEEE TO TMS320C3x CONVERSION (FAST VERSION) SUBROUTINE FMIEEE FUNCTION: CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x FLOATING-POINT FORMAT. THE NUMBER TO BE CONVERTED IS IN THE LOWER 32 BITS OF R0.
Page 123 Floating-Point Conversion (IEEE Std. 754) Example 5–4.IEEE-to-TMS320C3x Conversion (Fast Version) (Continued) NOTE: SINCE THE STACK POINTER SP IS USED, MAKE SURE TO INITIALIZE IT IN THE CALLING PROGRAM. CYCLES: 12 (WORST CASE) WORDS: 12 .global FMIEEE FMIEEE AND3 ADDI LDIZ...
Page 124: Floating-Point Format
Example 5–5. IEEE-to-TMS320C3x Conversion (Complete Version) TITLE IEEE TO TMS320C3x CONVERSION (COMPLETE VERSION) SUBROUTINE FMIEEE1 FUNCTION: CONVERSION BETWEEN THE IEEE FORMAT AND THE TMS320C3x FLOATING-POINT FORMAT. THE NUMBER TO BE CONVERTED IS IN THE LOWER 32 BITS OF R0. THE RESULT IS STORED IN THE UPPER 32 BITS OF R0.
Page 125 Floating-Point Conversion (IEEE Std. 754) Example 5–5.IEEE-to-TMS320C3x Conversion (Complete Version) (Continued) HANDLE NaN AND INFINITY TSTB *+AR1(7),R0 RETSNZ R0,R0 LDFGT *+AR1(8),R0 LDFN *+AR1(5),R0 RETS HANDLE 0s AND UNNORMALIZED NUMBERS UNNORM TSTB *+AR1(6),R0 LDFZ *+AR1(3),R0 RETSZ *+AR1(6),R0 NEG1 1,R0 SUBI *+AR1(2),R0...
Page 126: Converting 2S-Complement Tms320C3X Floating-Point Format To Ieee Format
5.4.2 Converting 2s-Complement TMS320C3x Floating-Point Format to IEEE Format This conversion is performed according to the following table: Table 5–2. Converting 2s-Complement Floating-Point Format to IEEE Format If these values are present Case –128 –127 –126 e –126 e –126 e †...
Page 127 Example 5–6. TMS320C3x-to-IEEE Conversion (Fast Version) TITLE TMS320C3x TO IEEE CONVERSION (FAST VERSION) SUBROUTINE TOIEEE FUNCTION: CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE FLOATING-POINT FORMAT. THE NUMBER TO BE CONVERTED IS IN THE UPPER 32 BITS OF R0. THE RESULT WILL BE IN THE LOWER 32 BITS OF R0.
Page 128 Example 5–6.TMS320C3x-to-IEEE Conversion (Fast Version) (Continued) CYCLES: 14 (WORST CASE) .global TOIEEE TOIEEE R0,R0 LDFZ *+AR1(4),R0 ABSF 1,R0 PUSHF R0 ADDI *+AR1(2),R0 1,R0 RETS ADDI *+AR1(2),R0 1,R0 ADDI *+AR1(3),R0 RETS Floating-Point Conversion (IEEE Std. 754) WORDS: 15 Determine the sign of the number...
Page 129 Example 5–7. TMS320C3x-to-IEEE Conversion (Complete Version) TITLE TMS320C3x TO IEEE CONVERSION (COMPLETE VERSION) SUBROUTINE TOIEEE1 FUNCTION: CONVERSION BETWEEN THE TMS320C3x FORMAT AND THE IEEE FLOATING-POINT FORMAT. THE NUMBER TO BE CONVERTED IS IN THE UPPER 32 BITS OF R0. THE RESULT WILL BE IN THE LOWER 32 BITS OF R0.
Page 130 Example 5–7.TMS320C3x-to-IEEE Conversion (Complete Version) (Continued) TOIEEE1 LDFZ ABSF PUSHF R0 ADDI CONT TSTB RETSNZ TSTB RETSZ PUSH POPF PUSHF R0 ADDI RETS ADDI ADDI RETS R0,R0 Determine the sign of the number *+AR1(4),R0 If 0, load appropriate number Branch to NEG if negative (delayed)
Page 131: Floating-Point Multiplication
Floating-Point Multiplication 5.5 Floating-Point Multiplication A floating-point number can be written in floating-point format as in the following formula, where ( man ) is the mantissa and ( exp ) is the exponent: The product of thus: c ( man ) = c ( exp ) = During floating-point multiplication, source operands are in the single-precision floating-point format.
Page 132 If c ( exp ) has overflowed (step 11) in the positive direction, then step 14 sets c ( exp ) to the most positive extended-precision format value. If c ( exp ) has overflowed in the negative direction, then step 14 sets c ( exp ) to the most negative extended-precision format value.
Page 133: Flowchart For Floating-Point Multiplication
Floating-Point Multiplication Figure 5–16. Flowchart for Floating-Point Multiplication c ( man ) = ( man ) x b ( man ) c ( man ) = 0 c ( exp ) =– 128 If c ( man ) > 0, set c ( exp ) to most positive value If c ( man ) <...
Page 134 Example 5–8 through Example 5–12 illustrate how floating-point multiplication is performed on the ’C3x. For these examples, the implied most significant nonsign bit is made explicit. Example 5–8. Floating-Point Multiply (Both Mantissas = –2.0) Let: b = –2.0 Where: single-precision floating-point format. Then: 0100.000000000000000000000000000000000000000000000 To place this number in the proper normalized format, it is necessary to shift...
Page 135 Floating-Point Multiplication Example 5–9. Floating-Point Multiply (Both Mantissas = 1.5) Let: b = 1.5 Where: a and b are both represented in binary form according to the single-preci- sion floating-point format. Then: x 10.00000000000000000000000 To place this number in the proper normalized format, it is necessary to shift the mantissa one place to the right and add 1 to the exponent.
Page 136 Example 5–11. Floating-Point Multiply Between Positive and Negative Numbers Let: b = –2.0 x 2 Then: x 10.00000000000000000000000 2 1110.0000000000000000000000000000000000000000000000 The result is: Example 5–12. Floating-Point Multiply by 0 All multiplications by a floating-point 0 yield a result of 0 ( f = 0, s = 0, and exp = –128).
Page 137: Floating-Point Addition And Subtraction
Floating-Point Addition and Subtraction 5.6 Floating-Point Addition and Subtraction In floating-point addition and subtraction, two floating-point numbers can be defined as: b = b ( man ) The sum (or difference) of Figure 5–17 shows the flowchart for floating-point addition. Because this flow- chart assumes signed data, it is also appropriate for floating-point subtraction.
Page 138: Flowchart For Floating-Point Addition
Figure 5–17. Flowchart for Floating-Point Addition (14) ( man ) b ( man ) Align mantissas ( man ) = ( man ) > > d Discard LSBs to keep ( man ) in extended- precision floating- point format Add mantissas c ( man ) = ( man ) + b ( man ) Test for special cases of c ( man ) Overflow of c ( man )
Page 139 Floating-Point Addition and Subtraction The following examples describe the floating-point addition and subtraction operations. It is assumed that the data is in the extended-precision floating- point format. Example 5–13. Floating-Point Addition In the case of two normalized numbers to be summed, let b = 0.5 = 01.0000000000000000000000000000000 It is necessary to shift b to the right by 1 so that and b have the same exponent.
Page 140 Example 5–14. Floating-Point Subtraction A subtraction is performed in this example. Let: b = 01.0000000000000000000000000000000 The operation performed is – b . The mantissas are already aligned because the two numbers have the same exponent. The result is a large cancellation of the upper bits, as shown below.
Page 141 Floating-Point Addition and Subtraction Example 5–16. Floating-Point Addition/Subtraction With Floating-Point 0 When floating-point addition and subtraction are performed with a floating- point 0, the following identities are satisfied: 0 – 5-36 0 = 0 = – (...
Page 142: Normalization Using The Norm Instruction
5.7 Normalization Using the NORM Instruction The NORM instruction normalizes an extended-precision floating-point number that is assumed to be unnormalized (see Example 5–17). Since the number is assumed to be unnormalized, no implied most significant nonsign bit is assumed. The NORM instruction: 1) Locates the most significant nonsign bit of the floating-point number 2) Left shifts to normalize the number 3) Adjusts the exponent...
Page 143: Flowchart For Norm Instruction Operation
Normalization Using the NORM Instruction Figure 5–18. Flowchart for NORM Instruction Operation 5-38 Test for special cases of c ( man ) ( man ) = 0 Leading nonsignificant sign bits c ( exp ) = –128 Sign-extended ( man ) 1 bit c ( man ) = ( man ) <...
Page 144: Rounding (Rnd Instruction)
5.8 Rounding (RND Instruction) The RND instruction rounds a number from the extended-precision floating- point format to the single-precision floating-point format. Rounding is similar to floating-point addition. Given the number a to be rounded, the following opera- tion is performed first. c = ( man ) Next, a conversion from extended-precision floating-point to single-precision floating-point format is performed.
Page 145: Flowchart For Floating-Point Rounding By The Rnd Instruction
Rounding (RND Instruction) Figure 5–19. Flowchart for Floating-Point Rounding by the RND Instruction c ( man ) = 0 c ( exp ) = –128 5-40 ( exp ) – 24 Add ( man ) and 1/2 of LSB c ( man ) = ( man ) + 2 –...
Page 146: Floating-Point To Integer Conversion (Fix Instruction)
5.9 Floating-Point to Integer Conversion (FIX Instruction) Using the FIX instruction, you can convert an extended-precision floating- point number to a single-precision integer in a single cycle. The floating-point to integer conversion of the value x is referred to here as fix( x ). The conversion does not overflow if a , the number to be converted, is in the range: –...
Page 147: Flowchart For Floating-Point To Integer Conversion By Fix Instruction
Floating-Point to Integer Conversion (FIX Instruction) Figure 5–20. Flowchart for Floating-Point to Integer Conversion by FIX Instruction If ( man ) > 0, c = most positive integer If ( man ) < 0, c = most negative integer 5-42 Test for special cases of ( exp ) ( exp ) >...
Page 148: Integer To Floating-Point Conversion (Float Instruction)
5.10 Integer to Floating-Point Conversion (FLOAT Instruction) Integer to floating-point conversion, using the FLOAT instruction, allows single-precision integers to be converted to extended-precision floating-point numbers. The flowchart for this conversion is shown in Figure 5–21. Figure 5–21. Flowchart for Integer to Floating-Point Conversion by FLOAT Instruction c ( man ) = 0 c ( exp ) = –128 Integer to Floating-Point Conversion (FLOAT Instruction)
Page 149 Fast Logarithms on a Floating-Point Device 5.11 Fast Logarithms on a Floating-Point Device The following TMS320C30/C40 function calculates the log base two of a number in about half the time of conventional algorithms. Furthermore, the method can easily be scaled for faster execution if less accuracy is desired. The method is efficient because the algorithm uses the floating-point multipliers’...
Page 150: Example Of Fast Logarithm On A Floating-Point Device
N * l og 2 (mant_old) = EXP_new + log 2 (mant_new) log 2 (mant_old) = EXP_new / N + l og 2 (mant_new) / N This last equation shows that the logarithm of mant_old is indeed related to EXP_new. And as shown earlier, EXP_new can be separated from the new mantissa and used as the logarithm of the original mantissa.
Page 151: Tabulated Values For Mantissa
Fast Logarithms on a Floating-Point Device are equivalent to the seven MSBs of the logarithm. If the exponent could hold all the bits needed for full accuracy, then it would be possible to continue the op- eration for all 24 bits of the mantissa. Since there are only eight bits in the expo- nent and the MSBs are used for negative values, only seven iterations are pos- sible before the exponent must be off-loaded and reinitialized to zero.
Page 152: Points To Consider
Fast Logarithms on a Floating-Point Device When finished, the bits representing the finished logarithm are in a fixed-point notation and need to be scaled. This is done by using the FLOAT instruction fol- lowed by a multiplication by a constant scaling factor. If the final result needs to be in any other base, the scaling factor is simply adjusted for that base.
Page 153: Fast Logarithm For Fft Displays
Fast Logarithms on a Floating-Point Device Figure 5–23. Fast Logarithm for FFT Displays **************************************************************** * FAST Logarithm for FFT displays >>>> NEED ONLY ADD ONE INSTRUCTION IN MANY CASES ****************************************************************** MPYF REAL,REAL,R0 MYPF IMAG,IMAG,R1 ADDF R1,R0 –1,R0 R0,OUT ********************************************************************** * _log_E.asm ********************************************************************** .global_log_E _log_E:POP...
Page 154: Addressing Modes
The ’C3x supports five groups of powerful addressing modes. Six types of addressing that allow data access from memory, registers, and the instruction word can be used within the groups. This chapter describes the operation, encoding, and implementation of the addressing modes. It also discusses the management of system stacks, queues, and dequeues in memory.
Page 155: Addressing Types
Addressing Types 6.1 Addressing Types You can access data from memory, registers, and the instruction word by using five types of addressing: Register addressing . A CPU register contains the operand. Direct addressing . The data address is formed by concatenating the eight least significant bits (LSBs) of the data-page (DP) register and the 16 LSBs of the instruction.
Page 156: Register Addressing
6.2 Register Addressing In register addressing, a CPU register contains the operand, as shown in this example: ABSF The syntax for the CPU registers, the assembler syntax, and the assigned function for those registers are listed in Table 6–1. Table 6–1. CPU Register Address/Assembler Syntax and Function Register Name ;...
Page 157: Direct Addressing
Direct Addressing 6.3 Direct Addressing In direct addressing, the data address is formed by the concatenation of the eight LSBs of the data-page pointer (DP) with the 16 LSBs of the instruction word (expr). This results in 256 pages (64K words per page), allowing you to access a large address space without requiring a change of the page pointer.
Page 158: Indirect Addressing
6.4 Indirect Addressing Indirect addressing specifies the address of an operand in memory through the contents of an auxiliary register, optional displacements, and index registers as shown in Example 6–2. Only the 24 LSBs of the auxiliary registers and index registers are used in indirect addressing.
Page 159: Indirect Addressing Operand Encoding
Indirect Addressing Figure 6–2. Indirect Addressing Operand Encoding Note: Auxiliary Register The auxiliary register (AR n ) is encoded in the instruction word according to its binary representation n (for example, AR3 is encoded as 11 machine address (shown in Table 6–1). 5 bits 3 bits disp...
Page 160: Indirect Addressing
Table 6–2. Indirect Addressing (a) Indirect addressing with displacement Mod Field Syntax 00000 *+AR n ( disp ) *– AR n ( disp ) 00001 00010 *++AR n ( disp ) 00011 *– – AR n ( disp ) 00100 *AR n ++( disp ) 00101 *AR n –...
Page 161: Indirect Addressing
Indirect Addressing Table 6–2. Indirect Addressing (Continued) (c) Indirect addressing with index register IR1 Mod Field Syntax 10000 *+ AR n (IR1) 10001 * – AR n (IR1) 10010 * ++ AR n (IR1) 10011 * – – AR n (IR1) * AR n ++ (IR1) 10100 *AR n –...
Page 162 Example 6–3. Indirect Addressing With Predisplacement Add The address of the operand to fetch is the sum of an auxiliary register (AR n ) and the displacement ( disp ). The displacement is either an 8-bit unsigned integer contained in the instruction word or an implied value of 1. Operation: Assembler Syntax: Modification Field:...
Page 163 Indirect Addressing Example 6–5. Indirect Addressing With Predisplacement Add and Modify The address of the operand to fetch is the sum of an auxiliary register (AR n ) and the displacement ( disp ). The displacement is either an 8-bit unsigned integer contained in the instruction word or an implied value of 1.
Page 164 Example 6–7. Indirect Addressing With Postdisplacement Add and Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the displacement ( disp ) is added to the auxiliary register.
Page 165 Indirect Addressing Example 6–9. Indirect Addressing With Postdisplacement Add and Circular Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the displacement ( disp ) is added to the contents of the auxiliary register using circular addressing.
Page 166 Example 6–11. Indirect Addressing With Preindex Add The address of the operand to fetch is the sum of an auxiliary register (AR n ) and an index register (IR0 or IR1). Operation: Assembler Syntax: Modification Field: IR m Example 6–12. Indirect Addressing With Preindex Subtract The address of the operand to fetch is the difference of an auxiliary register (AR n ) and an index register (IR0 or IR1).
Page 167 Indirect Addressing Example 6–13. Indirect Addressing With Preindex Add and Modify The address of the operand to fetch is the sum of an auxiliary register (AR n ) and an index register (IR0 or IR1). After the data is fetched, the auxiliary register is updated with the generated address.
Page 168 Example 6–15. Indirect Addressing With Postindex Add and Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the index register (IR0 or IR1) is added to the auxiliary register. Operation: Assembler Syntax: Modification Field:...
Page 169 Indirect Addressing Example 6–17. Indirect Addressing With Postindex Add and Circular Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the index register (IR0 or IR1) is added to the auxiliary register.
Page 170 Example 6–19. Indirect Addressing With Postindex Add and Bit-Reversed Modify The address of the operand to fetch is the contents of an auxiliary register (AR n ). After the operand is fetched, the index register (IR0) is added to the auxiliary register.
Page 171: Immediate Addressing
Immediate Addressing 6.5 Immediate Addressing In immediate addressing, the operand is a 16-bit (short) or 24-bit (long) immediate value contained in the 16 or 24 LSBs of the instruction word (expr). Depending on the data types assumed for the instruction, the short-immediate operand can be a 2s-complement integer, an unsigned integer, or a floating-point number.
Page 172: Pc-Relative Addressing
6.6 PC-Relative Addressing Program counter (PC)-relative addressing is used for branching. It adds the contents of the 16 or 24 LSBs of the instruction word to the PC register. The assembler takes the src (a label or address) specified by the user and generates a displacement.
Page 173: Encoding For 24-Bit Pc-Relative Addressing Mode
PC-Relative Addressing Figure 6–3. Encoding for 24-Bit PC-Relative Addressing Mode (a) BR, BRD: unconditional branches (standard and delayed) 0 1 1 0 0 0 0 0 (b) CALL: unconditional subroutine call 0 1 1 0 0 0 1 0 (c) RPTB: repeat block 0 1 1 0 0 1 0 0 6-20 25 24 23...
Page 174: Circular Addressing
6.7 Circular Addressing Many DSP algorithms, such as convolution and correlation, require a circular buffer in memory. In convolution and correlation, the circular buffer acts as a sliding window that contains the most recent data to process. As new data is brought in, the new data overwrites the oldest data by increasing the pointer to the data through the buffer in counter-clockwise fashion.
Page 175: Logical And Physical Representation Of Circular Buffer After Writing Eight Values
Circular Addressing Figure 6–6. Logical and Physical Representation of Circular Buffer after Writing Eight Values a) Logical representation Start value 6 value 7 value 2 To implement a circular buffer in the ’C3x, the following criteria must be satis- fied (more than one circular buffer can be implemented on the ’C3x as long as the size of the buffers are identical): Specify the size of the circular buffer (R) by storing the length of the buffer in the block-size register (BK).
Page 176: Circular Buffer Implementation
In circular addressing, index refers to the K LSBs (from the K-bit boundary criteria) of the auxiliary register selected, and step is the quantity being added to or subtracted from the auxiliary register. Follow these two rules when you use cir- cular addressing: The step used must be less than or equal to the block size.
Page 177: Data Structure For Fir Filters
Circular Addressing Example 6–24. Circular Addressing *AR0 ++ (5)% *AR0 ++ (2)% *AR0 – – (3)% *AR0++(6)% *AR0 – – % *AR0 4th, 3rd Circular addressing is especially useful for the implementation of FIR filters. Figure 6–8 shows one possible data structure for FIR filters. Note that the ini- tial value of AR0 points to h(N –1), and the initial value of AR1 points to x(0).
Page 178 Example 6–25. FIR Filter Code Using Circular Addressing Impulse Response .sect ”Impulse_Resp” .float 1.0 .float 0.99 .float 0.95 .float 0.1 Input Buffer .usect ”Input_Buf”,128 .data HADDR .word H XADDR .word X .word 128 Initialization Filter RPTS MPYF3 *AR0++%,*AR1++%,R0 ADDF3 R0,R2,R2 ADDF HADDR @N,BK...
Page 179: Bit-Reversed Addressing
Bit-Reversed Addressing 6.8 Bit-Reversed Addressing The ’C3x can implement fast Fourier transforms (FFT) with bit-reversed ad- dressing. Whenever data in increasing sequence order is transformed by an FFT, the resulting data is presented in bit-reversed order. To recover this data in the correct order, certain memory locations must be swapped.
Page 180: Index Steps And Bit-Reversed Addressing
Example 6–26. Bit-Reversed Addressing Table 6–3 shows the relationship of the index steps and the four LSBs of AR2. You can find the four LSBs by reversing the bit pattern of the steps. Table 6–3. Index Steps and Bit-Reversed Addressing Step *AR2++(IR0)B ;...
Page 181: Aligning Buffers With The Tms320 Floating-Point Dsp Assembly Language Tools
Aligning Buffers With the TMS320 Floating-Point DSP Assembly Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools 6.9 Aligning Buffers With the TMS320 Floating-Point DSP Assembly Language Tools To align buffers to a K-bit boundary, you can use the .sect or .usect assembly directives to define a section in conjunction with the align memory allocation parameter of the sections directive of the linker command file.
Page 182: System And User Stack Management
6.10 System and User Stack Management The ’C3x provides a dedicated system-stack pointer (SP) for building stacks in memory. The auxiliary registers can also be used to build a variety of more general linear lists. This section discusses the implementation of the following types of linear lists: Stack The stack is a linear list for which all insertions and deletions are made at...
Page 183: Stacks
System and User Stack Management 6.10.2 Stacks Stacks can be built from low to high memory or high to low memory. Two cases for each type of stack are shown. Stacks can be built using the preincrement/ decrement and postincrement/decrement modes of modifying the auxiliary registers (AR).
Page 184: Queues
Figure 6–11.Implementations of Low-to-High Memory Stacks AR n 6.10.3 Queues A queue is like a FIFO. The implementation of queues is based on the manipu- lation of auxiliary registers. Two auxiliary registers are used: one to mark the front of the queue from which data is popped (or dequeued) and the other to mark the rear of the queue where data is pushed.
Page 185: Program Flow Control
Program Flow Control The TMS320C3x provides a complete set of constructs that facilitate software and hardware control of the program flow. Software control includes repeats, branches, calls, traps, and returns. Hardware control includes reset operation, interrupts, and power management. You can select the constructs best suited for your particular application.
Page 186: Repeat Modes
Repeat Modes 7.1 Repeat Modes The repeat modes of the ’C3x can implement zero-overhead looping. For many algorithms, most execution time is spent in an inner kernel of code. Using the repeat modes allows these time-critical sections of code to be executed in the shortest possible time.
Page 187: Repeat-Mode Control Bits
7.1.1 Repeat-Mode Control Bits Two bits are important to the operation of RPTB and RPTS: RM bit. The repeat-mode (RM) flag bit in the status register specifies whether the processor is running in the repeat mode. S bit. The S bit is internal to the processor and cannot be programmed, but this bit is necessary to fully describe the operation of RPTB and RPTS.
Page 188: Rptb Instruction
Repeat Modes Example 7–1. Repeat-Mode Control Algorithm if RM == 1 if S == 1 if first time through fetch instruction from memory else fetch instruction from IR RC – 1 if RC < 0 ST(RM) PC + 1 else if S == 0 fetch instruction from memory if PC == RE RC –...
Page 189 All block repeats initiated by RPTB can be interrupted. When RPTB src (source) instruction executes, it performs the following sequence: 1) Load the start address of the block into repeat-start-address register (RS). This is the next address following the instruction: 2) Load the end address of the block into repeat-end-address register (RE).
Page 190: Repeat-Mode Restrictions
Repeat Modes The RPTS instruction loads all registers and mode bits necessary for the opera- tion of the single-instruction repeat mode. Step 1 loads the start address of the block into RS. Step 2 loads the end address into the RE (end address of the block).
Page 191: Rc Register Value After Repeat Mode Completes
Example 7–4. Incorrectly Placed Delayed Branch STLOOP ENDLOOP 7.1.6 RC Register Value After Repeat Mode Completes For the RPTB instruction, the RC register normally decrements to 0000 0000h unless the block size is 1; in which case, it decrements to FFFF FFFFh. However, if the RPTB instruction using a block size of 1 has a pipeline conflict in the instruc- tion being executed, the RC register decrements to 0000 0000h.
Page 192: Nested Block Repeats
Repeat Modes 7.1.7 Nested Block Repeats Block repeats (RPTB) can be nested. Since the registers RS, RE, RC, and ST control the repeat-mode status, these registers must be saved and restored in order to nest block repeats. For example, if you write an interrupt service routine that requires the use of RPTB, it is possible that the interrupt associated with the routine may occur during another block repeat.
Page 193: Delayed Branches
7.2 Delayed Branches The ’C3x offers three main types of branching: standard, delayed, and condi- tional delayed. Standard branches empty the pipeline before performing the branch, ensuring correct management of the program counter and resulting in a ’C3x branch taking four cycles. Included in this class are repeats, calls, returns, and traps. Delayed branches on the ’C3x do not empty the pipeline, but rather execute the next three instructions before the program counter is modified by the branch.
Page 194 Delayed Branches Example 7–6. Incorrectly Placed Delayed Branches For faster execution, it might still be advantageous to use a delayed branch followed by NOP instructions by trading increased program size for faster speed. This is shown in Example 7–7 where a NOP takes the place of the third unused instruction after the delayed branch.
Page 195: Calls, Traps, And Returns
7.3 Calls, Traps, and Returns Calls and traps provide a means of executing a subroutine or function while providing a return to the calling routine. The CALL, CALL cond, and TRAP cond instructions store the value of the PC on the stack before changing the PC’s contents. The RETS cond or RETI cond instructions use the value on the stack to return execution from traps and calls.
Page 196: Call Response Timing
Calls, Traps, and Returns RETI cond returns from traps or calls like the RETS cond , with the addition that RETI cond also sets the GIE bit of the status register, which enables all interrupts whose enabling bit is set to 1. The conditions for RETI cond are the same as for the CALL cond instruction.
Page 197: Interlocked Operations
7.4 Interlocked Operations One of the most common parallel processing configurations is the sharing of global memory by multiple processors. For multiple processors to access this global memory and share data in a coherent manner, some sort of arbitration or handshaking is necessary. This requirement for arbitration is the purpose of the ’C3x interlocked operations.
Page 198 Interlocked Operations The LDFI and LDII instructions perform the following actions: 1) Simultaneously set XF0 to 0 and begin a read cycle. The timing of XF0 is similar to that of the address bus during a read cycle. 2) Execute an LDF or LDI instruction and extend the read cycle until XF1 is set to 0 and a ready (RDY completes one H1/H3 cycle after the XF1 signal is detected.
Page 199 Note: Timing Diagrams for SIGI The timing diagrams for SIGI shown in the data sheets depict a zero wait state condition. Since the device idles until one cycle after XF1 is signaled, the data sheets show the XF1 signal sampled one H1/H3 cycle before setting the XF0 signal low.
Page 200 Interlocked Operations Example 7–8 shows the implementation of a busy-waiting loop. If location LOCK is the interlock for a critical section of code, and a nonzero means the lock is busy, the algorithm for a busy-waiting loop can be used as shown. Example 7–8.
Page 201: Multiple Tms320C3Xs Sharing Global Memory
Figure 7–2. Multiple TMS320C3xs Sharing Global Memory ’C3x #1 Sometimes it may be necessary for several processors to access some shared data or other common resources. The portion of code that must access the shared data is called a critical section. To ease the programming of critical sections, semaphores may be used.
Page 202: Zero-Logic Interconnect Of Tms320C3X Devices
Consider two processors connected as shown in Figure 7–3. The code for the two processors is shown in Example 7–12. Figure 7–3. Zero-Logic Interconnect of TMS320C3x Devices ’C3x #1 Processor #1 runs until it executes the SIGI. It then waits until processor #2 executes a SIGI.
Page 203 Example 7–12. Code to Synchronize Two TMS320C3x Devices at the Software Level Time 7.4.3 Pipeline Effects of Interlocked Instructions Before performing an interlocked instruction, the XF0 pin must be configured as an output pin and the XF1 pin must be configured as an input pin through the IOF register (see subsection 3.1.10, I/O Flag Register (IOF) , on page 3-16).
Page 204 Interlocked Operations Example 7–13. Pipeline Delay of XF Pin Configuration LDI 2h, IOF LDII *AR1, R1 XF1 sampled STFI and STII instructions drive the XF0 pin high during its execution phase. LDFI, LDII, and SIGI instructions sample the XF1 pin during its decode phase while driving the XF0 pin low during its read phase.
Page 205: Tms320C3X Pin Operation At Reset
Table 7–3 shows the state of the ’C3x’s pins after RESET = 0. Each pin is described according to whether the pin is reset synchronously or asynchronously. Table 7–3. TMS320C3x Pin Operation at Reset Signal Operation at Reset Primary Bus Interface Signals D31 –...
Page 206 Reset Operation Table 7–3. TMS320C3x Pin Operation at Reset (Continued) Signal Operation at Reset HOLDA Reset has no effect PRGW Reset has no effect Expansion Bus Interface XD31 – XD0 Synchronous reset; placed in high-impedance state XA12 – XA0 Synchronous reset; placed in high-impedance state XR/W Synchronous reset;...
Page 207 Table 7–3. TMS320C3x Pin Operation at Reset (Continued) Signal Operation at Reset Asynchronous reset; placed in high-impedance state FSR1 Asynchronous reset; placed in high-impedance state Timer0 Signal TCLK0 Asynchronous reset; placed in high-impedance state Timer1 Signal TCLK1 Asynchronous reset; placed in high-impedance state...
Page 208 Reset Operation Table 7–3. TMS320C3x Pin Operation at Reset (Continued) Signal Operation at Reset Emulation, Test, and Reserved EMU0 Undefined EMU1 Undefined EMU2 Undefined EMU3 Undefined EMU4 Undefined EMU5 Undefined EMU6 Undefined RSV0 Undefined RSV1 Undefined RSV2 Undefined RSV3 Undefined...
Page 209 At system reset, the following additional operations are performed: The peripherals are reset. This is a synchronous operation. Peripheral reset is described in Chapter 12, Peripherals . The external bus control registers are reset. The reset values of the control registers are described in Chapter 9, ’C30 and ’C31 External-Memory Interface .
Page 210 Interrupts 7.6 Interrupts The ’C3x supports multiple internal and external interrupts, which can be used for a variety of applications. Internal interrupts are generated by the DMA controller, timers, and serial ports. Four external maskable interrupt pins include INT0 – INT3.
Page 211 Table 7–4. Reset, Interrupt, and Trap-Vector Locations for the TMS320C30/ TMS320C31 Microprocessor Mode Address † Reserved on ’C31 Name Function RESET External reset signal input INT0 External interrupt on the INT0 pin INT1 External interrupt on the INT1 pin INT2 External interrupt on the INT2 pin INT3 External interrupt on the INT3 pin...
Page 212: Reset, Interrupt, And Trap-Branch Locations For The Tms320C31
Interrupts Table 7–5. Reset, Interrupt, and Trap-Branch Locations for the TMS320C31 Microcomputer Boot Mode Address 809FC1 809FC2 809FC3 809FC4 809FC5 809FC6 809FC7 809FC8 809FC9 809FCA 809FCB 809FCC–809FDF 809FE0 809FE1 809FFB 809FFC–809FFF 7-28 Name Function INT0 External reset signal input INT1 External interrupt on the INT0 pin INT2 External interrupt on the INT1 pin...
Page 213: Effective Base Address Of The Interrupt-Trap-Vector Table
7.6.2 TMS320C32 Interrupt Vector Table Similarly to the rest of the ’C3x device family, the ’C32’s reset vector location remains at address 0. On the other hand, the interrupt and trap vectors are relocatable. This is achieved by a new bit field in the CPU interrupt flag register called the interrupt-trap table pointer (ITTP), shown in Figure 3–11 on page 3-15.
Page 214: Interrupt And Trap-Vector Locations For The Tms320C32
Interrupts Table 7–6. Interrupt and Trap-Vector Locations for the TMS320C32 Address Name EA[ITTP] + 00h Reserved EA[ITTP] + 01h INT0 EA[ITTP] + 02h INT1 EA[ITTP] + 03h INT2 EA[ITTP] + 04h INT3 EA[ITTP] + 05h XINT0 EA[ITTP] + 06h RINT0 EA[ITTP] + 07h Reserved EA[ITTP] + 08h...
Page 215: Reset And Interrupt Vector Priorities
7.6.3 Interrupt Prioritization When two interrupts occur in the same clock cycle or when two previously received interrupts are waiting to be serviced, one interrupt is serviced before the other. The CPU handles this prioritization by servicing the interrupt with the least priority.
Page 216: Cpu Interrupt Control Bits
Interrupts 7.6.4 CPU Interrupt Control Bits Three CPU registers contain bits that control interrupt operation: Status (ST) register The CPU global interrupt-enable bit (GIE) located in the CPU status register (ST) controls all maskable CPU interrupts. When this bit is set to 1, the CPU responds to an enabled interrupt.
Page 217: If Register Modification
Figure 7–5. IF Register Modification Correct LDI @MASK, R0 AND R0, IF Note: IF Register Load Priority If a load of the IF register occurs simultaneously with a set or reset of a flag by an interrupt pulse, the loading of the flag has higher priority and overwrites the IF register value.
Page 218: Cpu Interrupt Processing
Interrupts Figure 7–6. CPU Interrupt Processing Complete all fetched instructions CPU starts executing ISR routine Note: CPU and DMA Interrupts CPU interrupts are acknowledged (responded to by the CPU) on instruction fetch boundaries only. If instruction fetches are halted because of pipeline conflicts or execution of RPTS loops, CPU interrupts are not acknowledged until the next instruction fetch.
Page 219 If you wish to make the interrupt service routine interruptible, you can set the GIE bit to 1 after entering the ISR. The interrupt acknowledge (IACK) instruction can be used to signal externally that an interrupt has been serviced. If external memory is specified in the operand, IACK drives the IACK pin and performs a dummy read.
Page 220: Interrupt Latency
Interrupts Table 7–8. Interrupt Latency Cycle Description Recognize interrupt in single-cycle fetched (prog a + 1) instruction Clear GIE bit. Clear interrupt flag Read the interrupt vector table Store return address to stack Pipeline begins to fill with ISR instruction Pipeline continues to fill with ISR instruction Pipeline continues to fill with ISR instruction Execute first instruction of interrupt service routine...
Page 221: Interrupt Logic Functional Diagram
Figure 7–7. Interrupt Logic Functional Diagram INTn These interrupts are prioritized by the selection of one over the other if both come on the same clock cycle (INT0 the highest, INT1 next, etc.). When an interrupt is taken, the status register ST(GIE) bit is reset to 0, disabling any other incoming interrupt.
Page 222: Dma Interrupts
DMA Interrupts 7.7 DMA Interrupts Interrupts can also trigger DMA read and write operations. This is called DMA synchronization. The DMA interrupt processing cycle is similar to that of the CPU. After the pertinent interrupt flag is cleared, the DMA coprocessor proceeds according to the status of the SYNC bits in the DMA coprocessor global-control register.
Page 223: Dma Interrupt Processing
7.7.2 DMA Interrupt Processing Figure 7–8 shows the general flow of interrupt processing by the DMA coprocessor. Figure 7–8. DMA Interrupt Processing For more information about DMA interrupts, see Section 12.3.7, DMA Interrupts on page 12-64. Is an enabled interrupt set If enabled in the IE register, the interrupt Is a DMA interrupt...
Page 224: Parallel Cpu And Dma Interrupt Processing
DMA Interrupts 7.7.3 CPU/DMA Interaction If the DMA is not using interrupts for synchronization of transfers, it is not affected by the processing of the CPU interrupts. Detected interrupts are responded to by the CPU and DMA on instruction fetch boundaries only. Since instruction fetches are halted due to pipeline conflicts or when executing instructions in an RPTS loop, interrupts are not responded to until instruction fetching continues.
Page 225: Tms320C3X Interrupt Considerations
7.7.4 TMS320C3x Interrupt Considerations Give careful consideration to ’C3x interrupts, especially if you make modifications to the status register when the global interrupt-enable (GIE) bit is set. This can result in the GIE bit being erroneously set or reset as described in the following paragraphs.
Page 226: Pipeline Operation With Push St
DMA Interrupts Table 7–9. Pipeline Operation with PUSH ST Cycle Description Read location V_ADDR Load AR1; recognize interrupt Clear GIE bit; clear interrupt flag; read SP Read interrupt vector table; save ST in stack Store return address on stack The following example shows setting the GIE bit by a load instruction that is immediately followed by an interrupt: interrupt recognized ––>MPYI In this example, the load of the status register or interrupt-flag register overwrites...
Page 227 One solution is to use an instruction that is uninterruptible such as RPTS as follows to set the GIE: RPTS Use the following to reset the GIE: RPTS Another alternative incorporates the following code fragment, which protects against modifying or saving the status register by disabling interrupts through the interrupt-enable register: PUSH IE In summary, the next three instructions immediately following an instruction...
Page 228: Tms320C30 Interrupt Considerations
DMA Interrupts 7.7.5 TMS320C30 Interrupt Considerations The ’C30 silicon revisions earlier than 4.0 have two unique exceptions to the interrupt operation. This does not apply to ’C30 silicon revision 4.0 or greater, any ’C31 silicon, or any ’C32 silicon. On ’C30 silicon revisions earlier than 4.0: The status register global interrupt-enable (GIE) bit may be erroneously reset to 0 (disabled setting) if all of the following conditions are true: During the decode phase of a conditional trap, interrupts are temporarily...
Page 229 DMA Interrupts Insert two NOP instructions immediately before the TRAP cond instruction. One NOP is insufficient in some cases, as illustrated in the second bulleted item, above. This eliminates the opportunity for any pipeline conflicts in the immediately preceding instructions and enables the conditional trap instruction to execute without delays.
Page 230 DMA Interrupts ISR_n: PUSH PUSH PUSH RETI ISR_n_START: . ISR_n_END: RETI 7-46 ; Save registers 0, DP ; Clear Data-page Pointer @DUMMY_INT, R0 ; If DUMMY_INT is 0 or positive, ISR_n_START ; go to ISR_n_START DP, @DUMMY_INT ; Set DUMMY_INT = 0 ;...
Page 231: Flow Of Traps
7.8 Traps A trap is the equivalent of a software-triggered interrupt. In the ’C3x, traps and interrupts are treated identically, except in the way in which they are triggered. 7.8.1 Initialization of Traps and Interrupts Traps and interrupts are triggered differently in the ’C3x: Traps are always triggered by a software mechanism, by the TRAP cond (conditional trap) instructions.
Page 232 Traps The RETI cond instruction manipulates the status flags as shown in block (3) in Figure 7–10. RETI cond provides a return from a trap or interrupt. The ’C3x supports 32 different traps. When a TRAP cond n instruction is executed, the ’C3x jumps to the address stored in the memory location pointed to by the corresponding trap-vector table pointer.
Page 233: Power Management Modes
7.9 Power Management Modes The following ’C3x devices have been enhanced by the addition of two power- down modes: IDLE2 and LOPOWER: ’C30 silicon version 7.0 or greater ’LC31 ’C31 silicon revision 5.0 or greater ’C32 7.9.1 IDLE2 Power-Down Mode The H1 instruction clock is held high until one of the four external interrupts is asserted.
Page 234: Idle2 Timing
Power Management Modes The interrupt service routine (ISR) must have been set up before placing the device in IDLE2 mode, because the instruction following the IDLE2 instruction is not executed until the RETI (return from interrupt) instruction is executed. When the device is in emulation mode, the H1 and H3 clocks continue to run normally and the CPU operates as if an IDLE instruction was executed.
Page 235: Interrupt Response Timing After Idle2 Operation
Figure 7–12. Interrupt Response Timing After IDLE2 Operation CLKIN INT3 to INT0 INT3 to INT0 Flag ADDR Data 7.9.2 LOPOWER In the LOPOWER (low-power) mode, the CPU continues to execute instructions, and the DMA can continue to perform transfers, but at a reduced clock rate of CLKIN frequency divided by 16.
Page 236: Lopower Timing
Power Management Modes Figure 7–13. LOPOWER Timing CLKIN Figure 7–14. MAXSPEED Timing CLKIN 7-52 LOPOWER read MAXSPEED read 32 CLKIN 32 CLKIN...
Page 237: Pipeline Operation
Two characteristics of the’C3x that contribute to its high performance are: Pipelining Concurrent I/O and CPU operation The following four functional units control ’C3x operation: Fetch Decode Read Execute Pipelining is the overlapping or parallel operations of the fetch, decode, read, and execute levels of a basic instruction.
Page 238: Tms320C3X Pipeline Structure
–1. The ‘C3x pipeline controller supports a high-speed processing rate of one execution per cycle. It also manages pipeline conflicts so that they are transparent to you. You do not need to take any special precautions to ensure correct operation. Figure 8–1. TMS320C3x Pipeline Structure CYCLE m–3 m–2 m–1...
Page 239 For ‘C30 and ‘C31, priorities from highest to lowest have been assigned to each of the functional units of the pipeline and to the DMA controller as follows: Execute (highest) Read Decode Fetch DMA (lowest) Despite the DMA controller’s low priority, you can minimize or even eliminate conflicts with the CPU through suitable data structuring because the DMA con- troller has its own data and address buses.
Page 240: Pipeline Conflicts
Pipeline Conflicts 8.2 Pipeline Conflicts Pipeline conflicts in the ’C3x can be grouped into the following categories: Branch conflicts Register conflicts Memory conflicts Each of these three types, including examples, is discussed in the following subsections. In these examples, when data is refetched or an operation is repeated, the symbol representing the stage of the pipeline is appended with a number.
Page 241 Example 8–1. Standard Branch Note: Both RPTS and RPTB flush the pipeline, allowing the RS, RE, and RC registers to be loaded at the proper time. If these registers are loaded without the use of RPTS or RPTB, no flushing of the pipeline occurs. Thus, RS, RE, and RC can be used as general-purpose 32-bit registers without pipeline conflicts.
Page 242: Register Conflicts
Pipeline Conflicts Example 8–2. Delayed Branch THREE MPYF 8.2.2 Register Conflicts Register conflicts involve reading or writing registers used for addressing. These conflicts occur when the pertinent register is not ready to be used. Some conditions under which you can avoid register conflicts are discussed in Sec- tion 8.3 on page 8-19.
Page 243 is loaded, and a different auxiliary register is used on the next instruction. Since the decode stage needs the result of the write to the auxiliary register, the decode of this second instruction is delayed two cycles. Every time the decode is delayed, a refetch of the program word is performed;...
Page 244: Memory Conflicts
Pipeline Conflicts In Example 8–4, two auxiliary registers are added together, with the result going to an extended-precision register. The next instruction uses a different auxiliary register as an address register. Example 8–4. A Read of ARs Followed by ARs for Address Generation NEXT Note: Loop counter auxiliary registers for the decrement and branch (DBR) instruc-...
Page 245 Memory pipeline conflicts consist of the following four types: Program wait Program fetch Incomplete A program fetch has begun but is not yet Execute only Hold everything These four types of memory conflicts are illustrated in examples and discussed in the paragraphs that follow. 8.2.3.1 Program Wait Two conditions can prevent the program fetch from beginning: The start of a CPU data access when:...
Page 246 Pipeline Conflicts Example 8–5. Program Wait Until CPU Data Access Completes Example 8–6 shows a program wait due to a multicycle data-data access or a multicycle DMA access. The ADDF, MPYF, and SUBF are fetched from some portion in memory other than the external port the DMA requires. The DMA begins a multicycle access.
Page 247 Example 8–6. Program Wait Due to Multicycle Access 8.2.3.2 Program Fetch Incomplete A program fetch incomplete occurs when an instruction fetch takes more than one cycle to complete because of wait states. In Example 8–7, the MPYF and ADDF are fetched from memory that supports single-cycle accesses. The SUBF is fetched from memory requiring one wait state.
Page 248 Pipeline Conflicts Example 8–7. Multicycle Program Memory Fetches n+2 RDY n+2 RDY Note: 8.2.3.3 Execute Only The execute-only type of memory pipeline conflict occurs when performing an interlocked load or when a sequence of instructions requires three CPU data accesses in a single cycle. There are two cases in which this occurs: An instruction performs a store and is followed by an instruction that performs two memory reads.
Page 249 Example 8–8. Single Store Followed by Two Reads Note: STFR 0,*AR1 ; R0 *AR2,R1 ; *AR2 *AR3,R2 ; *AR3 Pipeline Operation Fetch Decode — LDF LDF LDF LDF W, X, Y = Instruction representations Pipeline Conflicts *AR1 R1 in parallel with Read Execute —...
Page 250 Pipeline Conflicts Example 8–9 shows a parallel store followed by a single load or read. Since two parallel stores are required, the next CPU data-memory read must wait one cycle before beginning. One program-memory refetch can occur. Example 8–9. Parallel Store Followed by Single Read The final case involves an interlocked load (LDII or LDFI) instruction and XF1 = 1.
Page 251 Example 8–10. Interlocked Load 8.2.3.4 Hold Everything Three situations result in hold-everything memory pipeline conflicts: A CPU data load or store cannot be performed because an external port is busy. An external load takes more than one cycle. Conditional calls and traps, which take one more cycle than conditional branches, are processed.
Page 252 Pipeline Conflicts Example 8–11. Busy External Port Note: The second type of hold-everything conflict involves multicycle data reads. The read has begun and continues until completed. In Example 8–12, the LDF is performed from an external memory that requires several cycles to access. 8-16 R0,@DMA1 @DMA2,R0...
Page 253 Example 8–12. Multicycle Data Reads Note: The final type of hold-everything conflict deals with conditional calls (CALL cond ) and traps (TRAP cond ), which are different from other branch instructions. Whereas other branch instructions are conditional loads, the conditional calls and traps are conditional stores, which take one more cycle to complete than conditional branches (see Example 8–13).
Page 254 Pipeline Conflicts Example 8–13. Conditional Calls and Traps n+2/CALLaddr Note: 8-18 Pipeline Operation Fetch Decode CALL cond — CALL cond (nop) (nop) (nop) (nop) (nop) (nop) (nop) I = Instruction representation Read Execute — — — — CALL cond — CALL cond (nop) PC store...
Page 255: Resolving Register Conflicts
8.3 Resolving Register Conflicts If the auxiliary registers (AR7–AR0), the index registers (IR1–IR0), data-page pointer (DP), or stack pointer (SP) are accessed for any reason other than address generation, pipeline conflicts associated with the next memory access can occur. The pipeline conflicts and delays are presented in Section 8.2 on page 8-4.
Page 256 Resolving Register Conflicts Example 8–15. Write to an AR Followed by an AR for Address Generation Without a Pipeline Conflict 8-20 @TABLE,AR2 MPYF @VALUE,R1 ADDF R2,R1 MPYF *AR2++,R1 SUBF Pipeline Operation Fetch Decode Read — — MYPF — ADDF MYPF MYPF ADDF MYPF...
Page 257 Example 8–16. Write to DP Followed by a Direct Memory Read Without a Pipeline Conflict TABLE_ADDR *–AR3(2),R1 @TABLE_ADDR,AR0 PUSHF R6 PUSH Pipeline Operation Fetch Decode Read — — — PUSHF PUSH PUSHF Resolving Register Conflicts Execute — — DP written —...
Page 258: One Program Fetch And One Data Access For Maximum Performance
Memory Access for Maximum Performance 8.4 Memory Access for Maximum Performance If program fetches and data accesses are performed so that the resources being used cannot provide the necessary bandwidth, the pipeline is stalled until the data accesses are complete. Certain configurations of program fetch and data accesses yield conditions under which the ’C3x can achieve maximum throughput.
Page 259: One Program Fetch And Two Data Accesses For Maximum Performance
Table 8–2. One Program Fetch and Two Data Accesses for Maximum Performance Primary Bus Case No. Accesses 1 program 1 data 1 data — — — 1 program 1 DMA † The expansion bus is available only on the ’C30. Memory Access for Maximum Performance Accesses From Dual-Access Internal Memory...
Page 260: Minor Clock Periods
Clocking Memory Accesses 8.5 Clocking Memory Accesses This section discusses the role of internal clock phases (H1 and H3) and how the ’C3x handles multiple-memory accesses. The previous section discusses the interaction between sequences of instructions; this section discusses the flow of data on an individual instruction basis.
Page 261 See Chapter 6, Addressing Modes , for more information. As discussed in Chapter 7, the number of bus cycles for external memory accesses differs in some cases from the number of CPU execution cycles. For external reads, the number of bus cycles and CPU execution cycles is identical. For external writes, there are always at least two bus cycles, but unless there is a port-access conflict, there is only one CPU execution cycle.
Page 262 Clocking Memory Accesses If both source operands are to be fetched from memory, then memory reads can occur in several ways: If both operands are located in internal memory, the src1 read is performed during H3 and the src2 read during H1, completing two memory reads in a single cycle.
Page 263 Example 8–17. Dummy sr2 Read R0,*AR6 ADDI3 *AR1,*AR3,R0 Fetch ADDI3 Two cycles are required for the MSTRB store. Two additional cycles are required for the dummy MSTRB read of *AR3 (because a read follows a write). One cycle is required for an actual MSTRB read of *AR3. ;...
Page 264 Clocking Memory Accesses Example 8–18. Operand Swapping Alternative Switch the operands of the 3-operand instruction so that the internal read is performed first. ADDI3 Fetch Decode ADDI3 ADDI3 8-28 R0,*AR6 ; AR6 points to MSTRB space *AR3,*AR1,R0 ; AR3 points to on-chip RAM ( src 2) ;...
Page 265: Multiply Or Cpu Operation With A Parallel Store
8.5.2.3 Operations with Parallel Stores The next class of instructions includes every instruction that has a store in parallel with another instruction. Bits 31 and 30 for these instructions are equal to 1 1. The instruction word format for operations that perform a multiply or ALU opera- tion in parallel with a store is shown in Figure 8–5.
Page 266: Parallel Multiplies And Adds
Clocking Memory Accesses If dst1 and dst2 are both written to external memory, a single CPU cycle is still all that is necessary to complete the stores. In this case, four bus cycles are required. 1) In the first cycle, both dst1 and dst2 are written to the port, and the ex- a) The store for dst1 is completed on the second cycle.
Page 267: Tms320C30 And Tms320C31 External-Memory Interface
TMS320C30 and TMS320C31 External-Memory Interface This chapter describes the ’C30 and ’C31 external-memory interface. See Chapter 10, Enhanced External-Memory Interface , for detailed information on the ’C32 external bus operation. Memories and external peripheral devices are accessible through two external interfaces on the ’C30: Primary bus Expansion bus...
Page 268 Overview 9.1 Overview The ’C30 provides two external interfaces: the primary bus and the expansion bus. The TMS320C31 provides one external interface: the primary bus. The primary bus consists of a 32-bit data bus, a 24-bit address bus, and a set of control signals.
Page 269: Memory Interface Signals
9.2 Memory Interface Signals This section describes the differences between the ’C30 and ’C31 memory interface signals. 9.2.1 TMS320C30 Memory Interface Signals The TMS320C30 has two sets of control signals as follows: Primary bus control signals: STRB, R/W, HOLD, HOLDA, RDY Table 9–1 lists and describes the signals.
Page 270: Primary Bus Interface Signals
Memory Interface Signals Table 9–1. Primary Bus Interface Signals † Signal Type Description STRB Primary interface access strobe Specifies memory read (active high) or write (active low) mode HOLD Hold external memory interface HOLDA Hold acknowledge for external memory interface Indicates external primary interface is ready to be accessed A (23–0)
Page 271: Expansion Bus Interface Signals
Table 9–2. Expansion Bus Interface Signals † Signal Type Description MSTRB Expansion bus memory access strobe IOSTRB Expansion bus peripheral-access strobe XR/W Specifies memory (active high) or write (active low) mode XRDY Indicates external expansion interface is ready to be accessed XA (12–0) Expansion address bus.
Page 272: Memory-Mapped External Interface Control Registers
Memory Interface Signals Figure 9–1. Memory-Mapped External Interface Control Registers Peripheral Address 808060h 808061h 808062h 808063h 808064h 808065h 808066h 808067h 808068h 808069h 80806Ah 80806Bh 80806Ch 80806Dh 80806Fh Expansion-bus control (’C30 only) Reserved Reserved Reserved Primary-bus control (’C30, ’C31) Reserved Reserved Reserved Reserved Reserved...
Page 273: Primary-Bus Control Register
9.3 Memory Interface Control Registers Two memory interface control registers, the primary-bus control register and the expansion-bus control register, are described in this section. 9.3.1 Primary-Bus Control Register The primary bus control register is a 32-bit register that contains the control bits for the primary bus (see Figure 9–2).
Page 274: Primary-Bus Control Register Bits
Memory Interface Control Registers Table 9–3. Primary-Bus Control Register Bits Abbreviation Reset Value HOLDST NOHOLD WTCNT BNKCMP 10000 Name Description Hold status bit This bit signals whether the port is being held (HOLDST = 1) or is not being held (HOLDST = 0).
Page 275: Expansion-Bus Control Register
9.3.2 Expansion-Bus Control Register The expansion-bus control register is a 32-bit register that contains control bits for the expansion bus (see Figure 9–3 and Table 9–4). Figure 9–3. Expansion-Bus Control Register 31–16 15–12 Notes: 1) xx = reserved bit, read as 0 2) R = read, W = write Table 9–4.
Page 276 Programmable Wait States 9.4 Programmable Wait States The ’C3x has its own internal software-configurable ready-generation capability for each strobe. This software wait-state generator is controlled by configuring two bit fields in the primary or expansion bus interface control registers. Use the WTCNT field to specify the number of software wait-states to generate and use the SWW field to select one of the following four modes of wait-state generation: External RDY wait states are generated solely by the external RDY line...
Page 277: Wait-State Generation
Table 9–5. Wait-State Generation Inputs SWW Bit Field /RDYext Output /RDYwtcnt /RDYint TMS320C30 and TMS320C31 External-Memory Interface Programmable Wait States Functional Description Wait until external RDY is signaled Wait until internal wait state generator counts down to 0 Wait until first signal: external RDY or the internal wait state generator (logical OR) Wait until both external RDY is signaled and wait state generator counts down to...
Page 278: Bnkcmp Example
Programmable Bank Switching 9.5 Programmable Bank Switching Programmable bank switching allows you to switch between external memory banks without having to insert wait states externally due to memories that require several cycles to turn off. Bank switching is implemented on the primary bus only. The size of a bank is determined by the number of bits specified by the BNKCMP field of the primary bus control register.
Page 279 Programmable Bank Switching The ’C3x has an internal register that contains the MSBs (as defined by the BNKCMP field) of the last address used for a read or write over the primary inter- face. At reset, the register bits are set to 0. If the MSBs of the address being used for the current primary interface read do not match those contained in this internal register, a read cycle is not asserted for one H1/H3 clock cycle.
Page 280: Bank-Switching Example
Programmable Bank Switching Figure 9–5. Bank-Switching Example STRB Read Note: After changing BNKCMP, up to three instructions are fetched before the change in the bank size occurs. 9-14 Read Extra cycle Read...
Page 281: External Memory Interface Timing
9.6 External Memory Interface Timing This section discusses functional timing of operations on the primary bus and the expansion bus, the two independent parallel buses or the ’C3x devices. The parallel buses implement three mutually exclusive address spaces distin- guished through the use of three separate control signals: STRB, MSTRB, and IOSTRB.
Page 282 External Memory Interface Timing The (M)STRB signal is low for the active portion of both reads and writes. The active portion lasts one H1 cycle. Additionally, before and after the active portion ((M)STRB low) of writes only, there is a transition cycle of H1. This transition cycle consists of the following sequence: 1) (M)STRB is high.
Page 283: Read-Read-Write For (M)Strb
Figure 9–6. Read-Read-Write for (M)STRB = 0 (M)STRB (X)R/W (X)A Read (X)D (X)RDY Note: (x) RDY is sampled low on rising edge of H1. Data is read next falling edge of H1. Note: Back-to-Back Read Operations (M)STRB remains low during back-to-back read operations. Read TMS320C30 and TMS320C31 External-Memory Interface External Memory Interface Timing...
Page 284: Write-Write-Read For (M)Strb
External Memory Interface Timing Figure 9–7 illustrates a write-write-read sequence for (M)STRB active and no wait states. The address and data written are held valid approximately one-half cycle after (M)STRB changes. Figure 9–7. Write-Write-Read for (M)STRB = 0 (M)STRB (X)R/W (X)A Write data (X)D...
Page 285: Use Of Wait States For Read For (M)Strb
Figure 9–8 illustrates a read cycle with one wait state. Since (X)RDY = 1, the read cycle is extended. (M)STRB, (X)R/W, and (X)A are also extended one cycle. The next time (X)RDY is sampled, it is 0. Figure 9–8. Use of Wait States for Read for (M)STRB = 0 (M)STRB XR/W (X)A...
Page 286: Use Of Wait States For Write For (M)Strb
External Memory Interface Timing Figure 9–9 illustrates a write cycle with one wait state. Since initially (X)RDY = 1, the write cycle is extended. (M)STRB, (X)R/W, and (X)A are extended one cycle. The next time (X)RDY is sampled, it is 0. Figure 9–9.
Page 287: Read And Write For Iostrb
9.6.2 Expansion-Bus I/O Cycles In contrast to primary bus and MSTRB cycles, IOSTRB reads and writes are both two cycles in duration (with no wait states) and exhibit the same timing. During these cycles, address always changes on the falling edge of H1, and IOSTRB is low from the rising edge of the first H1 cycle to the rising edge of the second H1 cycle.
Page 288: Read With One Wait State For Iostrb
External Memory Interface Timing Figure 9–11 illustrates a read with one wait state when IOSTRB is active, and Figure 9–12 illustrates a write with one wait state when IOSTRB is active. For each wait state added, IOSTRB, XR/W, and XA are extended one clock cycle. Writes hold the data on the bus one additional cycle.
Page 289: Write With One Wait State For Iostrb
Figure 9–12. Write With One Wait State for IOSTRB = 0 IOSTRB XR/W XRDY Write data Extra cycle TMS320C30 and TMS320C31 External-Memory Interface External Memory Interface Timing 9-23...
Page 290: Memory Read And I/O Write For Expansion Bus
External Memory Interface Timing Figure 9–13 through Figure 9–23 illustrate the various transitions between memory reads and writes, and I/O writes over the expansion bus. Figure 9–13. Memory Read and I/O Write for Expansion Bus MSTRB IOSTRB XR/W Memory address XRDY 9-24 Read...
Page 291: Memory Read And I/O Read For Expansion Bus
External Memory Interface Timing Figure 9–14. Memory Read and I/O Read for Expansion Bus MSTRB IOSTRB XR/W Memory address I/O address Read I/O read XRDY TMS320C30 and TMS320C31 External-Memory Interface 9-25...
Page 292: Memory Write And I/O Write For Expansion Bus
External Memory Interface Timing Figure 9–15. Memory Write and I/O Write for Expansion Bus MSTRB IOSTRB XR/W Memory address XRDY 9-26 Memory write I/O address I/O write...
Page 293: Memory Write And I/O Read For Expansion Bus
Figure 9–16. Memory Write and I/O Read for Expansion Bus MSTRB IOSTRB XR/W Memory address XRDY Memory write TMS320C30 and TMS320C31 External-Memory Interface External Memory Interface Timing I/O address I/O read 9-27...
Page 294: I/O Write And Memory Write For Expansion Bus
External Memory Interface Timing Figure 9–17. I/O Write and Memory Write for Expansion Bus MSTRB IOSTRB XR/W XRDY 9-28 I/O address I/O write Memory address Memory write...
Page 295: I/O Write And Memory Read For Expansion Bus
Figure 9–18. I/O Write and Memory Read for Expansion Bus MSTRB IOSTRB XR/W XRDY I/O address I/O write TMS320C30 and TMS320C31 External-Memory Interface External Memory Interface Timing Memory address Read 9-29...
Page 296: I/O Read And Memory Write For Expansion Bus
External Memory Interface Timing Figure 9–19. I/O Read and Memory Write for Expansion Bus MSTRB IOSTRB XR/W I/O address XRDY 9-30 Memory address I/O read Memory write...
Page 297: I/O Read And Memory Read For Expansion Bus
External Memory Interface Timing Figure 9–20. I/O Read and Memory Read for Expansion Bus MSTRB IOSTRB XR/W I/O address Memory address I/O read Read XRDY TMS320C30 and TMS320C31 External-Memory Interface 9-31...
Page 298: I/O Write And I/O Read For Expansion Bus
External Memory Interface Timing Figure 9–21. I/O Write and I/O Read for Expansion Bus MSTRB IOSTRB XR/W XRDY 9-32 I/O address I/O write I/O address I/O read...
Page 299: I/O Write And I/O Write For Expansion Bus
External Memory Interface Timing Figure 9–22. I/O Write and I/O Write for Expansion Bus MSTRB IOSTRB XR/W I/O address I/O address I/O write I/O write XRDY TMS320C30 and TMS320C31 External-Memory Interface 9-33...
Page 300: I/O Read And I/O Read For Expansion Bus
External Memory Interface Timing Figure 9–23. I/O Read and I/O Read for Expansion Bus MSTRB IOSTRB XR/W XRDY 9-34 I/O address I/O read I/O address I/O read...
Page 301: Inactive Bus States For Iostrb
Figure 9–24 and Figure 9–25 illustrate the signal states when a bus is inactive (after an IOSTRB or (M)STRB access, respectively). The strobes (STRB, MSTRB and IOSTRB) and (X)R/W) go to 1. The address is driven with last exter- nal bus access, and the ready signal (XRDY or RDY) is ignored. Figure 9–24.
Page 302: Inactive Bus States For Strb And Mstrb
External Memory Interface Timing Figure 9–25. Inactive Bus States for STRB and MSTRB (M)STRB (X)R/W (X)A Write data (X)D (X)RDY ignored (X)RDY Bus inactive 9-36...
Page 303: Hold And Holda Timing
9.6.3 Hold Cycles Figure 9–26 illustrates the timing for HOLD and HOLDA. HOLD is an external asynchronous input. There is a minimum of one cycle delay from the time when the processor recognizes HOLD = 0 until HOLDA = 0. When HOLDA = 0, the address, data buses, and associated strobes are placed in a high-impedance state.
Page 304 TMS320C32 Enhanced External Memory The ’C32 external memory interface provides greater flexibility by improving the ’C3x core with several new features. This chapter describes these features and enhancements in detail. Topic 10.1 TMS320C32 Memory Features 10.2 TMS320C32 Memory Overview 10.3 Configuration .
Page 305: Tms320C32 Memory Features
TMS320C32 Memory Features 10.1 TMS320C32 Memory Features The ’C32 external memory interface includes the following features: One external pin, PRGW, configures the external-program-memory width to 16 or 32 bits. Two sets of memory strobes (STRB0 and STRB1) and one IOSTRB allow zero glue-logic interface to two banks of memory and one bank of external peripherals.
Page 306: Tms320C32 Memory Overview
10.2 TMS320C32 Memory Overview The following sections describe examples, control register setups, and restrictions necessary to fully understand the operation and functionality of the external memory interface. 10.2.1 External Memory Interface Overview The ’C32 memory interface accesses external memory through one 24-bit address and one 32-bit data bus that is shared by three mutually-exclusive strobes (STRB0, STRB1, and IOSTRB).
Page 307: Memory Address Spaces
TMS320C32 Memory Overview IOSTRB can access 32-bit data from 32-bit wide memory. It does not have the flexibility of STRB0 and STRB1 since it is composed of a single signal: IOSTRB. IOSTRB bus cycles are different from those of STRB0 and STRB1 and are discussed in Section 10.10.
Page 308: Status Register
The PRGW status bit field of the CPU status (ST) register reflects the setting of the PRGW pin. Figure 10–2 depicts all the bit fields of the CPU status (ST) register. Figure 10–2. Status Register 31–16 PRGW status config Notes: 1) xx = reserved bit, read as 0 The status of the PRGW pin also affects the reset value of the physical memory width bit fields of the STRB0 and STRB1 bus-control registers.
Page 309 TMS320C32 Memory Overview 10.2.3.2 16- or 32-Bit Floating-Point Data Types The ’C32 supports 16- or 32-bit floating point data. For 16-bit floating-point reads, the eight MSBs are the signed exponent and the eight LSBs are the signed mantissa (see Section 5.3.2, ’C32 Short Floating-Point Format for External 16-Bit Data , on page 5-6).
Page 310: Memory-Mapped External Interface Control Registers
10.3 Configuration To access 8-, 16-, or 32-bit data (types) from 8-, 16-, or 32-bit wide memory, the memory interface of the ’C32 device uses either strobe STRB0 or STRB1 with four pins each. These pins serve as byte-enable and/or additional-address pins. In conjunction with a shifted version of the internal address presented to the exter- nal address, the ’C32 can select a single byte from one external memory location or combine up to four bytes from contiguous memory locations.
Page 311: Strb0 Control Register
Configuration 10.3.1.1 STRB0 Control Register The STRB0 control register (Figure 10–4) is a 32-bit register that contains the control bits for the portion of the external bus memory space that is mapped to STRB0. The following table lists the register bits with the bit names and functions. At the system reset, 0F10F8h is written to the STRB0 control register if the PRGW pin is logic low and 0710F8h is written to the STRB0 control register if the PRGW pin is logic high.
Page 312 The instruction immediately preceding a change in the data-size or memory-width bit fields should not perform a multicycle store. Do not follow a change in the data-size or memory-width bit fields with a store instruction. Also, do not perform a load in the next two instructions following a change in the data-size or memory-width bit fields 10.3.1.3 IOSTRB Control Register...
Page 313: Strb0, Strb1, And Iostrb Control Register Bits
Configuration Table 10–1 describes the bits in the STRBO, STRB1, and the IOSTRB control registers. Table 10–1. STRB0, STRB1, and IOSTRB Control Register Bits Reset Value Abbreviation Name HOLDST Hold status bit NOHOLD Port hold signal Internal hold Software wait mode WTCNT Software wait mode BNKCMP...
Page 314 Table 10–1. STRB0, STRB1, and IOSTRB Control Register Bits (Continued) Reset Value Abbreviation Name Physical (STRB0 and STRB1 memory width control registers only) Description Indicates the size of the physical memory connected to the device. The “reset” value depends on the status of the PRGW pin.
Page 315 Configuration Table 10–1. STRB0, STRB1, and IOSTRB Control Register Bits (Continued) Reset Value Abbreviation Name Sign ext/ (STRB0 and STRB1 zero-fill control registers only) STRB config STRB configuration STRB switch (STRB0 control regis- ter only) 10-12 Description Selects the method of converting 8- and 16-bit integer data into 32-bit integer data when transferring data from external memory to an internal register or memory location.
Page 316: Using Physical Memory Width And Data-Type Size Fields
Figure 10–7. STRB Configuration 10.3.2 Using Physical Memory Width and Data-Type Size Fields Consider a ’C32 connected to two banks of external memory. In this configura- tion, one bank is mapped to STRB0 while the other bank is mapped to STRB1. The STRB0 bank of memory is 32 bits wide and stores 32-bit data types.
Page 317: Data-Access Sequence For A Memory Configuration With Two Banks
Configuration By setting the bit fields of the STRB0 bus control register with a physical- memory width of 32 bits and a data type size of 32 bits, the external address referring to the STRB0 location is identical to the internal address used by the ‘C32 CPU.
Page 318 10.4 Programmable Wait States The ’C3x has its own internal software-configurable ready-generation capability for each strobe. This software wait-state generator is controlled by configuring two fields in the primary or expansion bus interface control registers. Use the WTCNT field to specify the number of software wait states to generate and use the SWW field to select one of the following four modes of wait-state generation: External RDY.
Page 319: Wait-State Generation
Programmable Wait States Table 10–3. Wait-State Generation Inputs SWW Bit Field /RDYext /RDYwtcnt 10-16 Output /RDYint Functional Description Wait until external RDY is signaled Wait until internal wait state generator counts down to 0 Wait until first signal: external RDY or the internal wait state generator (logical OR) Wait until both external RDY is signaled and wait state generator counts down to 0 (logical...
Page 320 10.5 Programmable Bank Switching Programmable bank switching allows you to switch between external memory banks without having to insert wait states externally due to memories that require several cycles to turn off. Bank switching is implemented on STRB0 and STRB1 only.
Page 321 Programmable Bank Switching The ’C3x has an internal register that contains the MSBs (as defined by the BNKCMP field) of the last address used for a read or write over the primary inter- face. At reset, the register bits are set to 0. If the MSBs of the address being used for the current primary interface read do not match those contained in this inter- nal register, a read cycle is not asserted for one H1/H3 clock cycle.
Page 322 Programmable Bank Switching Note: After changing BNKCMP, up to three instructions are fetched before the change in bank size occurs. TMS320C32 Enhanced External Memory Interface 10-19...
Page 323 32-Bit-Wide Memory Interface 10.6 32-Bit-Wide Memory Interface The ’C32 memory interface to 32-bit-wide external memory uses STRBx_B3 through STRBx_B0 pins as strobe-byte-enable pins as shown in Figure 10–10. In this manner, the ’C32 can read from, or write to, a single 32-, 16-, or 8-bit value from the external 32-bit-wide memory.
Page 324: Strobe Byte-Enable For 32-Bit-Wide Memory With 8-Bit Data-Type Size
Table 10–5. Strobe Byte-Enable for 32-Bit-Wide Memory With 8-Bit Data-Type Size Figure 10–11. Functional Diagram for 8-Bit Data-Type Size and 32-Bit External-Memory Width ’C32 Memory interface A 23 A 23 A 22 A 22 A 21 A 21 A 20 A 20 A 19 A 18...
Page 325: Example Of 8-Bit Data-Type Size
32-Bit-Wide Memory Interface For example, reading from or writing to memory locations 90 4000h to 90 4004h involves the pins listed in Table 10–6. Table 10–6. Example of 8-Bit Data-Type Size Internal Address Bus 904000h 904001h 904002h 904003h 904004h Case 2: 32-Bit-Wide Memory With 16-Bit Data-Type Size When the data-type size is 16 bits, the ’C32 shifts the internal address one bit to the right before presenting it to the external-address pins.
Page 326: Example Of 16-Bit Data-Type Size And 32-Bit-Wide External Memory
Figure 10–12. Functional Diagram for 16-Bit Data-Type Size and 32-Bit External-Memory Width ’C32 Memory interface Î Î Î A 23 A 22 Î Î Î Î Î Î Î Î Î A 21 Î Î Î Î Î Î Î Î Î...
Page 327 32-Bit-Wide Memory Interface Case 3: 32-Bit-Wide Memory With 32-Bit Data-Type Size When the data size is 32 bits, the ’C32 does not shift the internal address before presenting it to the external address pins. In this case, the memory interface copies the value of the internal address bus to the respective external- address pins.
Page 328: Example Of 32-Bit-Wide Memory With 32-Bit Data-Type Size
For example, reading or writing to memory locations 904000h to 904004h involves the pins listed in Table 10–9. Table 10–9. Example of 32-Bit-Wide Memory With 32-Bit Data-Type Size Internal Address Bus 904000h 904001h 904002h 904003h 904004h External Address Pins Active Strobe Byte Enable 904000h STRB1_B0, STRB1_B1, STRB1_B2, and STRB1_B3...
Page 329 16-Bit-Wide Memory Interface 10.7 16-Bit-Wide Memory Interface The ’C32 memory interface to 16-bit-wide external memory uses STRBx_B3 pin as an additional address pin, A strobe byte-enable pins as shown in Figure 10–14. Note that the external- memory address pins are connected to the ’C32 address pins A In this manner, the ’C32 can read/write a single 32-, 16-, or 8-bit value from the external 16-bit-wide memory.
Page 330: Strobe-Byte Enable Behavior For 16-Bit-Wide Memory With 8-Bit Data-Type Size
Table 10–10. Strobe-Byte Enable Behavior for 16-Bit-Wide Memory with 8-Bit Data-Type Size Figure 10–15. Functional Diagram for 8-Bit Data-Type Size and 16-Bit External-Memory Width ’C32 Memory interface For example, reading or writing to memory locations 4000h to 4004h involves the pins listed in Table 10–11. Internal A STRBx_B3/A –1...
Page 331: Example Of 8-Bit Data-Type Size And 16-Bit-Wide External Memory
16-Bit-Wide Memory Interface Table 10–11. Example of 8-Bit Data-Type Size and 16-Bit-Wide External Memory Internal External Address Bus Address Pins 4000h 1000h 4001h 1000h 4002h 1000h 4003h 1000h 4004h 1001h Case 5: 16-Bit-Wide Memory With 16-Bit Data-Type Size When the data-type size is 16 bits, the ’C32 shifts the internal address one bit to the right before presenting it to the external address pins.
Page 332: Example Of 16-Bit-Wide Memory With 16-Bit Data-Type Size
Figure 10–16. Functional Diagram for 16-Bit Data-Type Size and 16-Bit External-Memory Width ’C32 STRBx logic For example, reading or writing to memory locations 4000h to 4004h involves the pins listed in Table 10–12. Table 10–12. Example of 16-Bit-Wide Memory With 16-Bit Data-Type Size Internal External Address Bus...
Page 333 16-Bit-Wide Memory Interface Case 6: 16-Bit-Wide Memory with 32-Bit Data-Type Size When the data type size is 32 bits, the ’C32 does not shift the internal address before presenting it to the external address pins. In this case, the memory interface copies the value of the internal address bus to the respective external address pins.
Page 334: Example Of 16-Bit-Wide Memory With 32-Bit Data-Type Size
Table 10–13. Example of 16-Bit-Wide Memory With 32-Bit Data-Type Size Internal External Address Bus Address Pins 4000h 4000h 4000h 4001h 4001h 4001h 4002h 4002h 4002h 4003h 4003h 4003h 4004h 4004h 4004h STRB0_B3 / A Active Strobe Byte Enable –1 STRB0_B0 and STRB0_B1 STRB0_B0 and STRB0_B1 STRB0_B0 and STRB0_B1 STRB0_B0 and STRB0_B1...
Page 335 8-Bit-Wide Memory Interface 10.8 8-Bit-Wide Memory Interface ’C32 memory interface to an 8-bit wide external memory uses STRBx_B3 and STRBx_B2 pins as additional address pins, A using STRBx_B0 as strobe byte-enable pin as shown in Figure 10–18. The external-memory address pins are connected to the ’C32’s address pins or 8-bit value from the external 8-bit-wide memory.
Page 336: Example Of 8-Bit-Wide Memory With 8-Bit Data-Type Size
Figure 10–19. Functional Diagram for 8-Bit Data-Type Size and 8-Bit External-Memory Width For example, reading or writing to memory locations A04000h to A04004h involves the pins listed in Table 10–14. Table 10–14. Example of 8-Bit-Wide Memory With 8-Bit Data-Type Size Internal External Address Bus...
Page 337 8-Bit-Wide Memory Interface Case 8: 8-Bit Wide Memory With 16-Bit Data-Type Size When the data-type size is 16 bits, the ‘C32 shifts the internal address one bit to the right before presenting it to the external-address pins. In this shift, the memory interface copies the value of the internal-address A address pins A internal-address A...
Page 338: Example Of 8-Bit-Wide Memory With 16-Bit Data-Type Size
For example, reading or writing to memory locations A04000h to A04002h involves the pins listed in Table 10–15. Table 10–15. Example of 8-Bit-Wide Memory With 16-Bit Data-Type Size Internal External Address Bus Address Pins A04000h D02000h D02000h A04001h D02001h D02001h A04002h D02002h D02002h...
Page 339 8-Bit-Wide Memory Interface Figure 10–21. Functional Diagram for 32-Bit Data-Type Size and 8-Bit External-Memory Width 10-36 ’C32 Memory interface toggle toggle STRBx logic D(7 – 0) STRBx_B3/A –1 STRBx_B2/A –2 STRBx_B0 I / O(7 – 0)
Page 340: Example Of 32-Bit Data-Type Size And 8-Bit-Wide Memory
For example, reading or writing to memory locations A04000h to A04001h involves the pins listed in Table 10–16. Table 10–16. Example of 32-Bit Data-Type Size and 8-Bit-Wide Memory Internal External Address Bus Address Pins A04000h A04000h A04000h A04000h A04000h A04001h A04001h A04001h A04001h...
Page 341: External Ready Timing Improvement
External Ready Timing Improvement 10.9 External Ready Timing Improvement The ready (RDY) timing should relate to the H1 low signal as shown in Figure 10–22. This is equivalent to the ’C4x ready timing, which increases the time between valid address and the sampling of RDY. This facilitates the memory hardware interface by allowing a longer address decode-circuit response time to generate a ready signal.
Page 342: Bus Timing
10.10 Bus Timing This section discusses functional timing of operations on the external memory bus. Detailed timing specifications are contained in the TMS320C32 Data Sheet . The timing of STRB0 and STRB1 bus cycles is identical and discussed in subsection 10.10.1. The abbreviation STRBx is used in references that per- tain equally to STRB0 and STRB1.
Page 343 Bus Timing Figure 10–23. Read-Read-Write Sequence for STRBx Active STRBx Figure 10–24 shows a zero wait-state write-write-read sequence for STRBx active. During back-to-back writes, the data is valid when STRBx changes for the first write, but for subsequent writes the data is valid when the address changes. Figure 10–24.
Page 344 Figure 10–25 shows a one wait-state read sequence and Figure 10–26 shows the write sequence for STRBx active. On the first H1 cycle, RDY is high; therefore, the read or write sequence is extended for one extra cycle. On the second H1 cycle, RDY is low and the read or write sequence is terminated.
Page 345 Bus Timing Figure 10–26. One Wait-State Write Sequence for STRBx Active STRBx 10.10.2 IOSTRB Bus Cycles In contrast to STRB0 and STRB1 bus cycles, IOSTRB full speed (zero wait- state) reads and writes consume two H1 cycles. During these cycles, the IOSTRB signal is low from the rising edge of the first H1 cycle to the rising edge of the second H1 cycle.
Page 346 Figure 10–27 illustrates a zero wait-state read and write sequence for IOSTRB active. During writes, the data is valid when IOSTRB changes. Figure 10–27. Zero Wait-State Read and Write Sequence for IOSTRB Active IOSTRB Figure 10–28 depicts a one wait-state read sequence for IOSTRB active. Figure 10–29 shows a one wait-state write sequence for IOSTRB active.
Page 347 Bus Timing Figure 10–28. One Wait-State Read Sequence for IOSTRB Active IOSTRB Figure 10–29. One Wait-State Write Sequence for IOSTRB Active IOSTRB R / W Figure 10–30 and Figure 10–31 illustrate the transitions between STRBx reads and IOSTRB writes and reads, respectively. In these transitions, the ad- dress changes on the falling edge of the H1 cycle.
Page 348 Figure 10–30. STRBx Read and IOSTRB Write STRB0,1 IOSTRB R / W Figure 10–31. STRBx Read and IOSTRB Read STRB0,1 IOSTRB R / W Read Read TMS320C32 Enhanced External Memory Interface Bus Timing I/O Write I/O read 10-45...
Page 349 Bus Timing Figure 10–32 and Figure 10–33 illustrate the transitions between STRBx writes and IOSTRB writes and reads, respectively. In these transitions, the address changes on the falling edge of the H3 cycle. Figure 10–32. STRBx Write and IOSTRB Write STRBx IOSTRB Figure 10–33.
Page 350 Figure 10–34 through Figure 10–37 show the transitions between IOSTRB writes/reads and STRBx writes/reads. In these transitions, the address changes on the rising edge of the H3 cycle. Figure 10–34. IOSTRB Write and STRBx Write STRBx IOSTRB I/O write TMS320C32 Enhanced External Memory Interface Bus Timing Write 10-47...
Page 351 Bus Timing Figure 10–35. IOSTRB Write and STRBx Read STRBx IOSTRB Figure 10–36. IOSTRB Read and STRBx Write STRBx IOSTRB 10-48 I/O Write I/O read Read Write...
Page 352 Figure 10–37. IOSTRB Read and STRBx Read STRBx IOSTRB Figure 10–38 through Figure 10–40 illustrate the transitions between reads and writes. I/O Read TMS320C32 Enhanced External Memory Interface Bus Timing Read 10-49...
Page 353 Bus Timing Figure 10–38. IOSTRB Write and Read IOSTRB Figure 10–39. IOSTRB Write and Write IOSTRB 10-50 I/O write I/O write I/O write I/O read...
Page 354 Figure 10–40. IOSTRB Read and Read IOSTRB 10.10.3 Inactive Bus States Figure 10–41 and Figure 10–42 show the signal states when a bus becomes inactive after an IOSTRB or STRBx, respectively. The strobes (STRB0, STRB1, IOSTRB, and R / W) are deasserted going to a high level. The address bus preserves the last value and the ready signal (RDY) is ignored.
Page 355 Bus Timing Figure 10–42. Inactive Bus States Following STRBx Bus Cycle STRBx 10-52 I/O write Bus inactive RDY ignored...
Page 356 Using the TMS320C31 and TMS320C32 Boot Loaders The ’C31 and ’C32 have on-chip boot loaders that can load and execute pro- grams received from a host processor, standard memory devices (including EPROM), or via serial port. Topic 11.1 TMS320C31 Boot Loader 11.2 TMS320C32 Boot Loader Chapter 11 .
Page 357: Tms320C31 Boot Loader
TMS320C31 Boot Loader 11.1 TMS320C31 Boot Loader This section describes how to use the ’C31 microcomputer/boot loader (MCBL/ MP) function. This feature is unique to the ’C31 and ’C32, and is not available on the ’C30 devices. 11.1.1 TMS320C31 Boot-Loader Description The boot loader lets you load and execute programs that are received from a host processor, inexpensive EPROMs, or other standard memory devices.
Page 358: Boot-Loader Mode Selection
Table 11–1. Boot-Loader Mode Selection INT0 Figure 11–1.TMS320C31 Boot-Loader Mode-Selection Flowchart INT1 INT2 INT3 Loader Mode External memory External memory External memory 32-bit serial Begin Reset MCBL/MP = 1 register Serial-port load bit INT3 set? Memory load register bit INT0 from 1000h set? register...
Page 359 TMS320C31 Boot Loader 11.1.3 TMS320C31 Boot-Loading Sequence The following is the sequence of events that occur during the boot load of a source program. Table 11–2 shows the structure of the source program. 1) Select the boot loader by resetting the ’C31 while driving the MCBL / MP pin high and the corresponding INT3 –...
Page 360 Figure 11–2.Boot-Loader Memory-Load Flowchart Memory load Branch to address boot 1, boot 2, or boot 3 Determine mode 8, 16, or 32 Set memory configuration control word Load block size End of source program code (block size = 0)? Load destination address Block size = 0? Transfer data from...
Page 361 TMS320C31 Boot Loader Figure 11–3.Boot-Loader Serial-Port Load-Mode Flowchart Block size = 0? Wait for serial port input Transfer data from serial port to destination address Block size –1 Block size = 0? Branch to destination Wait for serial- address of first port input block loaded Load destination...
Page 362: Tms320C31 Boot Data Stream Structure
TMS320C31 Boot Loader 11.1.4 TMS320C31 Boot Data Stream Structure Table 11–2 shows the data stream structure. The data stream is composed of a header of 1 (serial-port load) or 2 (memory load) words and one or more blocks of source data. The boot loader uses this header to determine the physical memory width where the source program resides (memory load) and to configure the primary bus interface before source program boot load.
Page 363: Source Data Stream Structure
TMS320C31 Boot Loader Table 11–2. Source Data Stream Structure † Word Content Memory width (8, 16, or 32 bits) where source program resides 8h, 10h, or 20h, respectively Value to set the STRB control register Size of first data block. The block size is the number of 32-bit words in the data block.
Page 364 11.1.4.1 Examples of External TMS320C31 Memory Loads Table 11–3, Table 11–4, and Table 11–5 show memory images for byte-wide, 16-bit-wide, and 32-bit-wide configured memory (see Figure 4–2 on page 4-6). These examples assume the following: An INT0 signal was detected after reset was deasserted (signifying an external memory load from boot 1).
Page 365 TMS320C31 Boot Loader Table 11–4. 16-Bit-Wide Configured Memory Address 0x1000 0x1001 0x1002 0x1003 0x1004 0x1005 0x1006 0x1007 Table 11–5. 32-Bit-Wide Configured Memory Address 0x1000 0x1001 0x1002 0x1003 After reading the header, the loader transfers 0x IFF 32-bit words, beginning at a specified destination address 0x 809C00.
Page 366 11.1.4.2 Serial-Port Loading Boot loads, by way of the ’C31 serial port, are selected by driving the INT3 pin active (low) following reset. The loader automatically configures the serial port for 32-bit fixed-burst-mode reads. It is interrupt-driven by the frame synchro- nization receive (FSR) signal.
Page 367: Tms320C31 Interrupt And Trap Memory Maps
TMS320C31 Boot Loader Table 11–6. TMS320C31 Interrupt and Trap Memory Maps 11-12 Address Description 809FC1 INT0 809FC2 INT1 809FC3 INT2 809FC4 INT3 809FC5 XINT0 809FC6 RINT0 809FC7 XINT1 (Reserved) 809FC8 RINT1 (Reserved) 809FC9 TINT0 809FCA TINT1 809FCB DINT0 809FCC–809FDF Reserved 809FE0 TRAP0 809FE1...
Page 368 TMS320C31 Boot Loader 11.1.6 TMS320C31 Boot-Loader Precautions The boot loader builds a one-word-deep stack, starting at location 809801h. Avoid loading code at location 809801h. The interrupt flags are not reset by the boot-loader function. If pending interrupts are to be avoided when interrupts are enabled, clear the IF register before enabling interrupts.
Page 369: Tms320C32 Boot Loader
TMS320C32 Boot Loader 11.2 TMS320C32 Boot Loader This section describes how to use the ’C32 microcomputer/boot loader (MCBL/MP) functions. 11.2.1 TMS320C32 Boot-Loader Description The ’C32 boot loader is an enhanced version of that found in the ’C31. The boot loader can load and execute programs received from a host processor through standard memory devices (including EPROM), with and without handshake, or through the serial port.
Page 370: Boot-Loader Mode Selection
Table 11–7. Boot-Loader Mode Selection INT0 INT1 INT2 INT3 11.2.3 TMS320C32 Boot-Loading Sequence The following is the sequence of events that occur during the boot load of a source program. Table 11–2 shows the structure of the source program. 1) Select the boot loader by resetting the ’C32 while driving the MCBL/MP pin high and the corresponding INT3–INT0 pins low.
Page 371 TMS320C32 Boot Loader 4) Otherwise, the boot loader attempts a memory boot load. Figure 11–6 shows the boot-loader memory flow. If the IF register’s INT0 bit field is set, the source program is loaded from memory location 1000h. If the IF regis- ter’s INT1 bit field is set, the source program is loaded from memory location 810000h.
Page 372 Figure 11–4.TMS320C32 Boot-Loader Mode-Selection Flowchart Begin Reset MCBL/MP = 1 register bit Serial-port load INT3 set? Memory load register bit from 81000h INT1 set? Memory load register bit from 1000h INT0 set? Memory load register bit from 900000h INT2 set? Using the TMS320C31 and TMS320C32 Boot Loaders TMS320C32 Boot Loader 11-17...
Page 373 TMS320C32 Boot Loader Figure 11–5.Boot-Loader Serial-Port Load Flowchart Serial-port load Set up serial port for 32-bit fixed-burst mode Wait for serial-port Input Read IOSTRB control word Wait for serial-port Input Read STRB0 control word Wait for serial-port Input Read STRB1 control word 11-18 Wait for serial-port Input Load block size...
Page 374 Figure 11–6.Boot-Loader Memory-Load Flowchart Memory load IF register bit field INT3 Enable handshake mode Determine boot address: Boot 1, Boot 2, or Boot 3 Read memory width: 8, 16, or 32 bits Read IOSTRB control register Read STRB0 control register Read STRB1 control register Read block size...
Page 375 TMS320C32 Boot Loader Figure 11–7.Handshake Data-Transfer Operation Valid data D31-0 IACK 11.2.4 TMS320C32 Boot Data Stream Structure Table 11–8 shows the data stream structure. The data stream is composed of a header of three (serial-port load) or four (memory load) words and one or more blocks of source data.
Page 376: Source Data Stream Structure
Table 11–8. Source Data Stream Structure † Word Content Memory width (8, 16, or 32 bits) where source program resides Value to set the IOSTRB control register at end of boot loader process Value to set the STRB0 control register at end of boot loader process Value to set the STRB1 control register at end of boot loader process...
Page 377 TMS320C32 Boot Loader Table 11–8. Source Data Stream Structure (Continued) † Word Content m + 2 Last block destination memory width and data-type size in the format given in the Valid Data Entries column. m + 3 First word of last block. Last word of last source block j + 1 Zero word.
Page 378 11.2.5 Boot-Loader Hardware Interface The hardware interface for the memory boot load uses the STRBX_B3 through STRBX_B0 pins as strobe byte-enable pins (see Figure 11–8). The hardware interface is independent of the boot source memory width. This interface is identical to the 32-bit-wide memory interface described in Case 2, in Section 10.6 on page 10-20.
Page 379 TMS320C32 Boot Loader The ’C32 boot loader uses the following peripheral memory-mapped registers as a temporary stack: Timer0 counter register (808024h) Timer0 period register (808028h) DMA0 source address register (808004h) DMA0 destination address register (808006h) DMA0 transfer counter register (808008h) These memory-mapped registers are not reset by the boot-loading process.
Page 380 The ’C3x features two timers, a serial port (two serial ports for the ’C30), and an on-chip direct memory access (DMA) controller (2-channel DMA controller on the ’C32). These peripheral modules are controlled through memory- mapped registers located on the dedicated peripheral bus. The DMA controller performs input/output operations without interfering with the operation of the CPU, making it possible to interface the ’C3x to slow, exter- nal memories and peripherals, analog-to-digital converters (A/Ds), serial...
Page 381 Timers 12.1 Timers The ’C3x has two 32-bit general-purpose timer modules. Each timer has two signaling modes and internal or external clocking. You can use the timer modules to signal to the ’C3x or the external world at specified intervals or to count external events.
Page 382 12.1.1 Timer Pins Each timer has one pin associated with the timer clock signal (TCLK) pin. This pin (TCK) is used as a general-purpose I/0 signal, as a timer output, or as an input for an external clock for a timer. Each timer has a TCLK pin: TCLK0 is connected to timer0, TCLK1 to timer1.
Page 383: Timer Global-Control Register
Timers Figure 12–2. Memory-Mapped Timer Locations 12.1.3 Timer Global-Control Register The timer global-control register is a 32-bit register that contains the global and port control bits for the timer module. Figure 12–3 shows the format of the timer global-control register. Bits 3 – 0 are the port control bits; bits 11 –...
Page 384: Timer Global-Control Register Bits Summary
Table 12–1. Timer Global-Control Register Bits Summary Reset Abbreviation Name Value FUNC Function Input/output DATOUT Data output † DATIN Data input Counter hold signal † x = 0 or 1 (set to value read on TCLK) Description Controls the function of TCLK. If FUNC = 0, TCLK is configured as a general-purpose digital I/O port.
Page 385 Timers Table 12–1. Timer Global-Control Register Bits Summary (Continued) Reset Abbreviation Name Value Clock/pulse mode control CLKSRC Clock source Inverter control TSTAT Timer status bit † x = 0 or 1 (set to value read on TCLK) 12-6 Description When C/P = 1, clock mode is chosen, and the signal- ing of the TSTAT flag and external output has a 50% duty cycle.
Page 386 12.1.4 Timer-Period and Counter Registers The 32-bit timer-period register is used to specify the frequency of the timer signaling. The timer-counter register is a 32-bit register, which is reset to 0 whenever it increments to the value of the period register. Both registers are set to 0 at reset.
Page 387 Timers Figure 12–4. Timer Timing (a) TSTAT and timer output (INV = 0) when C/P = 0 (pulse mode) (b) TSTAT and timer output (INV = 0) when C/P = 1 (clock mode) The timer signaling is determined by the frequency of the timer input clock and the period register.
Page 388 Example 12–1. Timer Output Generation Examples 12H1 (a) INV = 0, C/P = 0 (pulse mode) timer period = 1 Also, INV = 0, C/P = 1 (clock mode) timer period = 0 (b) INV = 0, C/P = 0 (pulse mode) timer period = 2 INV = 0, C/P = 0 (pulse mode) timer period = 3...
Page 389 Timers 12.1.6 Timer Operation Modes The timer can receive its input and send its output in several different modes, depending upon the setting of CLKSRC, FUNC, and I/O. The four timer modes of operation are defined in the following sections. 12.1.6.1 CLKSRC = 1 and FUNC = 0 If CLKSRC = 1 and FUNC = 0, the timer input comes from the internal clock.
Page 390 12.1.6.2 CLKSRC = 1 and FUNC = 1 If CLKSRC = 1 and FUNC = 1 (see Figure 12–6), the timer input comes from the internal clock, and the timer output goes to TCLK. This value can be inverted using INV, and you can read in DATIN the value output on TCLK. Figure 12–6.
Page 391 Timers 12.1.6.4 CLKSRC = 0 and FUNC = 1 If CLKSRC = 0 and FUNC = 1 (see Figure 12–8), TCLK drives the timer. If INV = 0, all 0-to-1 transitions of TCLK increment the counter. If INV = 1, all 1-to-0 transitions of TCLK increment the counter. You can read in DATIN the value of TCLK.
Page 392 12.1.8 Timer Interrupts A timer interrupt is generated whenever the TSTAT bit of the timer control register changes from a 0 to a 1. The frequency of timer interrupts depends on whether the timer is set up in pulse mode or clock mode. In pulse mode, the interrupt frequency is determined by the following equation: (interrupt)
Page 393 Timers 2) Configure the timer through the timer global-control register (with GO = HLD = 0 ), the timer-counter register, and timer-period register, if necessary. 3) Start the timer by setting the GO/HLD bits of the timer global-control register. Example 12–2 shows how to set up the ‘C3x timer to generate the maximum clock frequency through the TCLKx pin.
Page 394: Serial Ports
12.2 Serial Ports The ’C30 has two totally independent bidirectional serial ports. Both serial ports are identical, and there is a complementary set of control registers in each one. Only one serial port is available on the ’C31 and the ’C32. You can configure each serial port to transfer 8, 16, 24, or 32 bits of data per word simultaneously in both directions.
Page 395 Serial Ports Figure 12–11. Serial Port Block Diagram RINT 12-16 Receive Section CLKR TSTAT Receive CLKR timer (16) Receive Clock Bit counter (8/16/24/32) (32) Load control Load (32) Transmit Section CLKX TSTAT Transmit CLKX timer (16) Bit counter (8/16/24/32) (32) Load Load control...
Page 396: Serial-Port Global-Control Register
Figure 12–12. Memory-Mapped Locations for the Serial Ports 808040h 808042h 808043h 808044h 808045h 808046h 808048h 80804Ch 808050h 808052h 808053h 808054h 808055h 808056h 808058h 80805Ch Note: † See Figure 12–13. ‡ See Figure 12–14. § See Figure 12–15. ¶ See Figure 12–16. # See Figure 12–17.
Page 397: Serial-Port Global-Control Register Bits Summary
Serial Ports Figure 12–13. Serial-Port Global-Control Register RRESET XRESET RINT CLKRP CLKXP RFSM XFSM Notes: 1) R = read, W = write 2) xx = reserved bit, read as 0 Table 12–2. Serial-Port Global-Control Register Bits Summary Reset Abbreviation Name Value RRDY Receive ready flag...
Page 398 Table 12–2. Serial-Port Global-Control Register Bits Summary (Continued) Reset Abbreviation Name Value Handshake XCLK SRCE Transmit clock source RCLK SRCE Receive clock source XVAREN Transmit data rate mode RVAREN Receive data rate mode XFSM Transmit frame sync mode RFSM Receive frame sync mode CLKXP CLKX polarity...
Page 399 Serial Ports Table 12–2. Serial-Port Global-Control Register Bits Summary (Continued) Reset Abbreviation Name Value CLKRP CLKR polarity DX polarity DR polarity FSXP FSX polarity FSRP FSR polarity XLEN Transmit word length RLEN Receive word length XTINT Transmit timer interrupt enable XINT Transmit interrupt enable...
Page 400 Table 12–2. Serial-Port Global-Control Register Bits Summary (Continued) Reset Abbreviation Name Value RINT Receive interrupt enable XRESET Transmit reset RRESET Receive reset Description If RINT = 0, the receive interrupt is disabled. If RINT = 1, the receive interrupt is enabled. Note: The CPU receive interrupt flag RINT and the serial- port-to-DMA interrupt (ERINT0 in the IE register) are the OR of the enabled receive timer interrupt and the enabled receive...
Page 401: Fsx/Dx/Clkx Port-Control Register Bits Summary
Serial Ports 12.2.2 FSX/DX/CLKX Port-Control Register This 32-bit port-control register controls the function of the serial port FSX, DX, and CLKX pins. The register is shown in Figure 12–14. Table 12–3 shows the register bits, bit names, and bit functions. Figure 12–14.
Page 402: Fsr/Dr/Clkr Port-Control Register
Table 12–3. FSX/DX/CLKX Port-Control Register Bits Summary (Continued) Reset Abbreviation Value FSX FUNC FSX function FSX I/O FSX input/output mode FSX DATOUT FSX data output † FSX DATIN FSX data input † x = 0 or 1 12.2.3 FSR/DR/CLKR Port-Control Register This 32-bit port-control register is controlled by the function of the FSR, DR, and CLKR pins.
Page 403: Fsr/Dr/Clkr Port-Control Register Bits Summary
Serial Ports Table 12–4. FSR/DR/CLKR Port-Control Register Bits Summary Reset Abbreviation Name Value CLKR FUNC Clock receive function CLKR I/O Clock receive input/output mode CLKR DATOUT Clock receive data output † CLKR DATIN Clock receive data input DR FUNC DR function DR I/O DR input/output mode...
Page 404: Receive/Transmit Timer-Control Register Register Bits Summary
12.2.4 Receive/Transmit Timer-Control Register A 32-bit receive/transmit timer-control register contains the control bits for the timer module. At reset, all bits are set to 0. Figure 12–16 shows the register. Bits 5 –0 control the transmitter timer. Bits 11 – 6 control the receiver timer. The serial port receive/transmit timer function is similar to timer module operation.
Page 405 Serial Ports Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued) Reset Abbreviation Name Value XCLKSRC Transmit clock source XTSTAT Transmit timer status Receive timer counter restart RHLD Receive counter hold signal RC/P Rclock/pulse mode control 12-26 Function Specifies the source of the transmit timer clock. When XCLKSRC = 1, an internal clock with frequency equal to one-half the CLKOUT frequency is used to increment the counter.
Page 406: Receive/Transmit Timer-Counter Register
Table 12–5. Receive/Transmit Timer-Control Register Register Bits Summary (Continued) Reset Abbreviation Name Value RCLKSRC Receive timer clock source RTSTAT Receive timer status 12.2.5 Receive/Transmit Timer-Counter Register The receive/transmit timer-counter register is a 32-bit register (see Figure 12–17). Bits 15–0 are the transmit timer-counter, and bits 31 – 16 are the receive timer-counter.
Page 407: Receive/Transmit Timer-Period Register
Serial Ports 12.2.6 Receive/Transmit Timer-Period Register The receive/transmit timer-period register is a 32-bit register (see Figure 12–18). Bits 15–0 are the timer transmit period, and bits 31–16 are the receive period. Each register specifies the period of the timer and is cleared to 0 at reset . Figure 12–18.
Page 408 Data is shifted to the left (LSB to MSB). Figure 12–20 illustrates what happens when words less than 32 bits are shifted into the serial port. In this figure, it is assumed that an 8-bit word is being received and that the upper three bytes of the receive buffer are originally undefined.
Page 409 Serial Ports Figure 12–21. Serial-Port Clocking in I/O Mode CLKX FUNC= 0 (I/O mode) CLKX I/O XCLK SRC = 1 (internal CLK for timer) TSTAT DATOUT CLKX FUNC= 0 (I/O mode) CLKX I/O XCLK SRC = 1 (internal CLK for timer) TSTAT DATOUT (NC) 12-30...
Page 410: Serial-Port Timing
Figure 12–22. Serial-Port Clocking in Serial-Port Mode CLKX FUNC= 1 (serial-port mode) CLKX I/O = 1 (output serial-port CLK) XCLK SRC = 0 or 1 TSTAT Timer DATOUT (NC) DATIN 12.2.10 Serial-Port Timing The formula for calculating the frequency of the serial-port clock with an inter- nally generated clock depends upon the operation mode of the serial-port timers, defined as: f (pulse mode) = f (timer clock)/period register...
Page 411 Serial Ports The transmit ready (XRDY) signal specifies that the data-transmit register (DXR) is available to be loaded with new data. XRDY goes active as soon as the data is loaded into the transmit-shift register (XSR). The last word may still be shifting out when XRDY goes active.
Page 412 12.2.10.1 Continuous Transmit and Receive Modes When you choose continuous mode, consecutive writes do not generate or expect new sync pulse signaling. Only the first word of a block begins with an active synchronization. Thereafter, data is transmitted as long as new data is loaded into DXR before the last word has been transmitted.
Page 413 Serial Ports When the serial port is placed in the handshake mode, the insertion and deletion of a leading 1 for transmitted data, the sending of a 0 for acknowledgement of received data, and the waiting for this acknowledge bit are all performed auto- matically.
Page 414 12.2.12 Serial-Port Functional Operation The following paragraphs and figures illustrate the functional timing of the various serial-port modes of operation. The timing descriptions are presented with the assumption that all signal polarities are configured to be positive (that is, CLKXP = CLKRP = DXP = DRP = FSXP = FSRP = 0). Logical timing, in situ- ations where one or more of these polarities are inverted, is the same except with respect to the opposite polarity reference points (that is, rising vs.
Page 415 Serial Ports 12.2.12.1 Fixed Data-Rate Timing Operation Fixed data-rate serial-port transfers can occur in two varieties: burst mode and continuous mode. In burst mode, transfers of single words are separated by periods of inactivity on the serial port. In continuous mode, there are no gaps between successive word transfers;...
Page 416 Figure 12–27. Fixed Standard Mode With Back-to-Back Frame Sync CLKX/R FSX (Internal) FSR/FSX (External) DR/DX DXR loaded with A For receive operations and with externally generated FSX, once transfers have begun, frame sync pulses are required only during the last bit trans- ferred to initiate another contiguous transfer.
Page 417 Serial Ports sync inputs are ignored. Additionally, you should set R/XFSM prior to or during the first word transferred; you must set R/XFSM no later than the transfer of the N –1 bit of the first word, except for transmit operations. For transmit operations in the fixed data-rate mode, XFSM must be set no later than the N –2 bit.
Page 418 Figure 12–29. Exiting Fixed Continuous Mode Without Frame Sync, FSX Internal CLKX (internal) LOAD DXR SET XFSM RESET XFSM 12.2.12.2 Variable Data-Rate Timing Operation The following variations are included in variable data-rate timing operations. Variable Burst Mode In burst mode with variable data-rate timing, FSX/FSR pulse lasts for the entire duration of transfer.
Page 419 Serial Ports Variable Standard Mode When you transmit continuously in variable data-rate mode with frame sync, timing is the same as for fixed data-rate mode, except for the differences between these two modes as described in Section 12.2.12 Serial-Port Functional Operation , on page 12-35. The only other exception is that you must reload DXR no later than the N –4 bit to maintain continuous opera- tion of the variable data-rate mode (see Figure 12–31);...
Page 420 XHLD and RHLD bits of the serial-port receive/transmit timer-control register, if necessary. 12.2.14 TMS320C3x Serial-Port Interface Examples In addition to the examples presented in this section, you can find DMA/serial port initialization examples in Example 12–9 and Example 12–10 on pages 12-76 and 12-77, respectively.
Page 421 Serial Ports 12.2.14.1 Handshake Mode Example When using the handshake mode, the transmit (FSX/DS/CLKX) and receive (FSR/DR/CLKR) signals transmit and receive data, respectively. Even if the ’C3x serial port is receiving data only with handshake mode, the transmit signals are still needed to transmit the acknowledge signal. Example 12–3 shows the serial-port register setup for the ’C3x serial-port handshake communication, as shown in Figure 12–25 on page 12-34.
Page 422 Example 12–4 and Example 12–5 are serial-port register setups for the above case. (Assume two ’C3xs have the same system clock.) Example 12–4. Serial-Port Register Setup #1 Global control Transmit port control Receive port control S_port timer control S_port timer count S_port timer period Example 12–5.
Page 423 Serial Ports Example 12–6. CPU Transfer With Serial Port Transmit Polling Method * TITLE: CPU TRANSFER WITH SERIAL-PORT TRANSMIT POLLING METHOD .GLOBAL START .DATA SOURCE .WORD _ARRAY .BSS _ARRAY,128 SPORT .WORD 808040H SPRESET .WORD 008C0044 SGCCTRL .WORD 048C0044H SXCTRL .WORD 111H TION STCTRL .WORD 00FH...
Page 424 12.2.14.4 Serial Analog Interface Chips Interface Example The TLC320C4x analog interface chips (AIC) from Texas Instruments offer a zero-glue-logic interface to the ’C3x family of DSPs. The interface is shown in Figure 12–33 as an example of the ’C3x serial-port configuration and operation.
Page 425 ’C3x family of DSPs. The interface is shown in Example 12–7. This interface is used as an example of the ’C3x serial port configuration and operation. Example 12–7. TMS320C3x Zero-Glue-Logic Interface to Burr Brown A/D and D/A Burr Brown DSP102 A/D 2.75 V 2.75 V...
Page 426 4) The bit clock drives both the A/D’s and D/A’s XCLK input. 5) The ’C3x transmit clock also acts as the input clock on the receive side of the ’C3x serial port. 6) Since the receive clock is synchronous to the internal clock of the ’C3x, the receive clock can run at full speed (that is, f(H1)/2).
Page 427: Dma Controller
DMA Controller 12.3 DMA Controller The DMA controller is a programmable peripheral that transfers blocks of data to any location in the memory map without interfering with CPU operation. The ’C3x can interface to slow, external memories and peripherals without reducing throughput to the CPU.
Page 428 12.3.1.1 TMS320C30 and TMS320C31 DMA Controller The ’C30 and ’C31 have an on-chip direct memory access (DMA) controller that reduces the need for the CPU to perform input/output functions. The DMA controller can perform input/output operations without interfering with the operation of the CPU.
Page 429 DMA Controller 12.3.2 DMA Basic Operation If a block of data is to be transferred from one region in memory to another region in memory (as shown in Figure 12–34), the following sequence is performed: DMA Registers Initialization 1) The source-address register of a DMA channel is loaded with the address of the memory location to read from.
Page 430: Dma Registers
After the completion of a block transfer, the DMA controller can be programmed to do several things: Stop until reprogrammed (TC = 1) Continue transferring data (TC = 0) Generate an interrupt to signal the CPU that the block transfer is complete (TCINT = 1) The DMA can be stopped by setting the START bits to 00, 01, or 10.
Page 431 DMA Controller At reset, each DMA-channel control register is set to 0. This makes the DMA channels lower-priority than the CPU, sets up the source address and destination address to be calculated through linear addressing, and configures the DMA channel in the unified mode. Figure 12–35.
Page 432 12.3.3.1 DMA Global-Control Register The global-control register controls the state in which the DMA controller operates. This register also indicates the status of the DMA, which changes every cycle. Source and destination addresses can be incremented, decrem- ented, or synchronized using specified global-control register bits. At system reset, all bits in the DMA control register are cleared to 0.
Page 433: Dma Global-Control Register Bits Summary
DMA Controller Table 12–6. DMA Global-Control Register Bits Summary Reset Abbreviation Name Value START DMA start control STAT DMA status 12-54 Description Controls the state in which the DMA starts and stops. The DMA may be stopped without any loss of data. The following table summarizes the START bits and DMA operation: Bit 1...
Page 434 Table 12–6. DMA Global-Control Register Bits Summary (Continued) Reset Abbreviation Name Value INCSRC DMA source address increment mode DECSRC DMA source address decrement mode INCDST DMA destination address increment mode DECDST DMA destination address decrement mode SYNC DMA synchronization mode DMA transfer mode TCINT DMA transfer counter...
Page 435 DMA Controller Table 12–6. DMA Global-Control Register Bits Summary (Continued) Reset Abbreviation Name Value DMA0 PRI CPU/DMA channel 0 priority mode CPU/DMA channel 1 DMA1 PRI priority mode PRIORITY DMA channels priority MODE mode 12-56 Description (on the DMA0 control register) (’C32 only) (on the DMA1 control register) (‘C32 only) Configures CPU/DMA controller priority.
Page 436 12.3.3.2 Destination-Address and Source-Address Registers The DMA destination-address and source-address registers are 24-bit registers whose contents specify destination and source addresses. As specified by control bits DECSRC, INCSRC, DECDST, and INCDST of the DMA global- control register, these registers are incremented, decremented, or remain unchanged at the end of the corresponding memory access;...
Page 437 DMA Controller 12.3.3.3 Transfer-Counter Register The transfer-counter register is a 24-bit register that contains the number of words to be transmitted. Figure 12–40 shows the transfer-counter operation. It is controlled by a 24-bit counter that decrements at the beginning of a DMA memory write.
Page 438 Figure 12–40. Transfer-Counter Operation 12.3.4 CPU/DMA Interrupt-Enable Register The CPU/DMA interrupt-enable register (IE) is a 32-bit register located in the CPU register file. The CPU interrupt-enable bits are in locations 10–1. The DMA interrupt-enable bits are in locations 26–16. A 1 in a CPU/DMA interrupt-enable register bit enables the corresponding interrupt.
Page 439 DMA Controller Figure 12–41. TMS320C30 and TMS320C31 CPU/DMA Interrupt-Enable Register 31 30 29 28 27 EDINT ETINT1 (DMA) (DMA) 15 14 13 12 11 EDINT ETINT1 (CPU) (CPU) Notes: 1) R = read, W = write 2) xx = reserved bit, read as 0 Figure 12–42.
Page 440: Cpu/Dma Interrupt-Enable Register Bits
Table 12–7. CPU/DMA Interrupt-Enable Register Bits Reset Abbreviation Value Description EINT0 (CPU) CPU external interrupt 0 enable EINT1 (CPU) CPU external interrupt 1 enable EINT2 (CPU) CPU external interrupt 2 enable EINT3 (CPU) CPU external interrupt 3 enable EXINT0 (CPU) CPU serial port 0 transmit interrupt enable ERINT0 (CPU) CPU serial port 0 receive interrupt enable...
Page 441: Tms320C32 Dma Internal Priority Schemes
DMA Controller Table 12–7. CPU/DMA Interrupt-Enable Register Bits (Continued) Abbreviation ETINT0 (DMA) ETINT1 (DMA) ETINT0 (DMA0) ETINT1 (DMA0) ETINT0 (DMA1) ETINT1 (DMA1) EDINT (DMA) EDINT1 (DMA0) EDINT0 (DMA1) EINT0 (DMA1) EINT1 (DMA1) EINT2 (DMA1) EINT3 (DMA1) 12.3.5 TMS320C32 DMA Internal Priority Schemes Because all accesses made by the two DMA channels take place over one common internal DMA data and address bus, a priority scheme for bus arbitra- tion is required.
Page 442 12.3.5.2 Rotating Priority Scheme In a rotating priority scheme, the last channel serviced becomes the lowest priority channel. The other channel sequentially rotates through the priority list with the lowest channel next to the last-serviced channel becoming the highest priority on the following request. The priority rotates every time the channel most recently granted priority completes its access.
Page 443: Tms320C32 Dma Pri Bits And Cpu/Dma Arbitration Rules
DMA Controller Table 12–8.TMS320C32 DMA PRI Bits and CPU/DMA Arbitration Rules DMA PRI (Bits 13–12) 12.3.7 DMA and Interrupts The DMA controller uses interrupts in the following way: It can send interrupts to the CPU or other DMA channel when a block transfer finishes.
Page 444 The DMA and the CPU can respond to the same interrupt if the CPU is not involved in any pipeline conflict or in any instruction that halts instruction fetching. Refer to section 7.6.2, Interrupt Vector Table and Prioritization , on page 7-29 for more details.
Page 445 DMA Controller Figure 12–44. Mechanism for DMA Source Synchronization Destination synchronization (SYNC = 1 0) When SYNC = 1 0, the DMA is synchronized to the destination. First, all interrupts are ignored until the read is complete. Though the DMA interrupts are considered globally disabled, no bits in the DMA interrupt-enable regis- ter are changed.
Page 446 Source and destination synchronization (SYNC = 1 1) When SYNC = 1 1, the DMA is synchronized to both the source and destination. A read is performed when an interrupt is received. Then, a write is performed on the following interrupt. Figure 12–46 shows source and destination synchronization when SYNC = 1 1.
Page 447 DMA Controller The data transfer rate for a DMA channel (assuming a single-channel access with no conflicts between CPU or other DMA channels) is as follows: On-chip memory and peripheral External memory (STRB, STRB0, STRB1, MSTRB) External memory (IOSTRB) If the DMA started and is transferring data over either external bus, do not modify the bus-control register associated with that bus.
Page 448 Figure 12–47. DMA Timing When Destination is On Chip Cycles (H1) Source on chip Destination on chip Source STRB, STRB0, STRB1, MSTRB bus Source STRB STRB0 STRB1 MSTRB bus Destination on chip Source IOSTRB bus Source IOSTRB bus Destination on chip Legend: = Number of transfers = Single-cycle writes...
Page 449 Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus Cycles (H1) Source on chip Destination STRB, STRB0, STRB1, MSTRB Source STRB, STRB0, STRB0 STRB1 Destination STRB, STRB, STRB0, STRB1 (’C30 only) Source Source IOSTRB Destination STRB bus Legend: = Number of transfers = Source-read wait states...
Page 450 Figure 12–48. DMA Timing When Destination is an STRB, STRB0, STRB1, MSTRB Bus (Continued) Cycles (H1) Source IOSTRB IOSTRB Destination STRB0, STRB1, or MSTRB (’C30 only) Source STRB bus Destination MSTRB Legend: = Number of transfers = Single-cycle writes = Source-read wait states = Multicycle reads C w = Destination-write wait states = Multicycle writes...
Page 451 Figure 12–49. DMA Timing When Destination is an IOSTRB Bus Cycles (H1) Source on chip Destination IOSTRB Destination IOSTRB (’C30 only) Source STRB bus Destination IOSTRB bus Destination IOSTRB bus Source STRB0, STRB1, MSTRB bus Destination IOSTRB Legend: = Number of transfers = Single-cycle writes = Source-read wait states = Multicycle reads...
Page 452 12.3.9 DMA Initialization/Reconfiguration You can control the DMA through memory-mapped registers located on the dedicated peripheral bus. Following is the general procedure for initializing and/or reconfiguring the DMA: 1) Halt the DMA by clearing the START bits of the DMA global-control register. You can do this by writing a 0 to the DMA global-control register.
Page 453 DMA Controller The transfer counter has a zero value. However, the transfer counter is decremented after the DMA read operation finishes (not after the write operation). Nevertheless, a transfer counter with a 0 value can be used as an indication of a transfer completion. The STAT bits in the DMA channel-control register are set to 00 poll the DMA channel-control register for this value.
Page 454 Example 12–8. Array Initialization With DMA * TITLE: ARRAY INITIALIZATION WITH DMA .GLOBAL START .DATA .WORD 808000H RESET .WORD 0C40H CONTROL .WORD 0C43H SOURCE .WORD ZERO DESTIN .WORD _ARRAY COUNT .WORD 128 ZERO .FLOAT 0.0 .BSS _ARRAY,128 .TEXT START LDP DMA LDI @DMA,AR0 LDI @RESET,R0 STI R0,*AR0...
Page 455 DMA Controller Example 12–9. DMA Transfer With Serial-Port Receive Interrupt * TITLE DMA TRANSFER WITH SERIAL PORT RECEIVE INTERRUPT .GLOBAL START .DATA .WORD 808000H CONTROL .WORD 0D43H SOURCE .WORD 80804CH DESTIN .WORD _ARRAY COUNT .WORD IEVAL .WORD 00200400H RESET1 .WORD 0D40H .BSS _ARRAY,128...
Page 456 Example 12–10 sets up the DMA to transfer data (128 words) from an array buffer to the serial port 0 output register with serial port transmit interrupt XINT0. The DMA sends an interrupt to the CPU when the data transfer completes. Serial port 0 is initialized to transmit 32-bit data words with an internally gener- ated frame sync and a bit-transfer rate of 8(H1) cycles/bit.
Page 457 DMA Controller Example 12–10. DMA Transfer With Serial-Port Transmit Interrupt (Continued) * DMA INITIALIZATION LDI @DMA,AR0 LDI @SPORT,AR1 LDI @RESET,R0 STI R0,*+AR1(4) STI R0,*AR0 STI R0,*AR1 LDI @SOURCE,R0 STI R0,*+AR0(4) LDI @DESTIN,R0 STI R0,*+AR0(6) LDI @COUNT,R0 STI R0,*+AR0(8) OR @IEVAL,IE OR 2000H,ST LDI @CONTROL,R0 STI R0,*AR0...
Page 458 Transfer a 128-word block of data from on-chip memory to off-chip memory and generate an interrupt on completion. Invert the memory or- der; the highest addressed member of the block is to become the lowest addressed member. DMA source address: DMA destination address: DMA transfer counter: DMA global control:...
Page 459 Assembly Language Instructions The ’C3x assembly language instruction set supports numeric-intensive, signal- processing, and general-purpose applications. (The addressing modes used with the instructions are described in Chapter 5.) The ’C3x instruction set can also use one of 20 condition codes with any of the 10 conditional instructions, such as LDF cond .
Page 460: Load And Store Instructions
Instruction Set 13.1 Instruction Set The ’C3x instruction set is well suited to digital signal processing and other numeric-intensive applications. All instructions are a single machine word long, and most instructions require one cycle to execute. In addition to multiply and accumulate instructions, the ’C3x possesses a full complement of general- purpose instructions.
Page 461: 2-Operand Instructions
13.1.2 2-Operand Instructions The ’C3x supports 35 2-operand arithmetic and logical instructions. The two operands are the source and destination. The source operand can be a memory word, a register, or a part of the instruction word. The destination operand is always a register.
Page 462: 3-Operand Instructions
Instruction Set 13.1.3 3-Operand Instructions Whereas 2-operand instructions have a single source operand (or shift count ) and a destination operand, 3-operand instructions can have two source operands (or one source operand and a count operand) and a destination operand. A source operand can be a memory word or a register.
Page 463: Program-Control Instructions
Table 13–4. Program-Control Instructions Instruction Description B cond Branch conditionally (standard) B cond D Branch conditionally (delayed) Branch unconditionally (standard) Branch unconditionally (delayed) CALL Call subroutine CALL cond Call subroutine conditionally DB cond Decrement and branch conditionally (standard) DB cond D Decrement and branch conditionally (delayed) IACK...
Page 464: Interlocked-Operations Instructions
Instruction Set Table 13–6. Interlocked-Operations Instructions Instruction Description LDFI Load floating-point value, interlocked LDII Load integer, interlocked SIGI Signal, interlocked 13.1.7 Parallel-Operations Instructions The 13 parallel-operations instructions make a high degree of parallelism possible. Some of the ’C3x instructions can occur in pairs that are executed in parallel.
Page 465 Table 13–7. Parallel Instructions (Continued) (a) Parallel arithmetic with store instructions (Continued) Mnemonic FLOAT LSH3 MPYF3 MPYI3 NEGF NEGI SUBF3 SUBI3 XOR3 Description Convert integer to floating-point value and store floating- point value Load floating-point value and store floating-point value Load integer and store integer Logical shift and store integer Multiply floating-point values and store floating-point value...
Page 466 Instruction Set Table 13–7. Parallel Instructions (Continued) (b) Parallel load instructions Mnemonic (c) Parallel multiply and add/subtract instructions Mnemonic MPYF3 ADDF3 MPYF3 SUBF3 MPYI3 ADDI3 MPYI3 SUBI3 These parallel instructions have been enhanced on the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater These devices support greater combinations of operands by also allowing the use of any CPU register whenever an indirect operand is required.
Page 467 13.1.8 Illegal Instructions The ’C3x has no illegal instruction-detection mechanism. Fetching an illegal (undefined) opcode can cause the execution of an undefined operation. Proper use of the TI TMS320 floating-point software tools will not generate an illegal opcode. Only the following conditions can cause the generation of an illegal opcode: Misuse of the tools An error in the ROM code...
Page 468: Instruction Set Summary
Instruction Set Summary 13.2 Instruction Set Summary Table 13–8 lists the ’C3x instruction set in alphabetical order. Each table entry provides the instruction mnemonic, description, and operation. Table 13–8. Instruction Set Summary Mnemonic Description ABSF Absolute value of a floating-point number ABSI Absolute value of an integer ADDC...
Page 469 Table 13–8. Instruction Set Summary (Continued) Mnemonic Description B cond Branch conditionally (standard) B cond D Branch conditionally (delayed) Branch unconditionally (standard) Branch unconditionally (delayed) CALL Call subroutine CALL cond Call subroutine conditionally CMPF Compare floating-point values CMPF3 Compare floating-point values (3-operand) CMPI Compare integers...
Page 470 Instruction Set Summary Table 13–8. Instruction Set Summary (Continued) Mnemonic Description DB cond Decrement and branch conditionally (standard) DB cond D Decrement and branch conditionally (delayed) Convert floating-point value to integer FLOAT Convert integer to floating-point value IACK Interrupt acknowledge IDLE Idle until interrupt IDLE2...
Page 471 Table 13–8. Instruction Set Summary (Continued) Mnemonic Description LDI cond Load integer conditionally LDII Load integer, interlocked Load floating-point mantissa Load data page pointer LOPOWER Divide clock by 16 Logical shift LSH3 Logical shift (3-operand) MAXSPEED Restore clock to regular speed MPYF Multiply floating-point values MPYF3...
Page 472 Instruction Set Summary Table 13–8. Instruction Set Summary (Continued) Mnemonic Description No operation NORM Normalize floating-point value Bitwise-logical complement Bitwise-logical OR Bitwise-logical OR (3-operand) Pop integer from stack POPF Pop floating-point value from stack PUSH Push integer on stack PUSHF Push floating-point value on stack RETI cond Return from interrupt conditionally...
Page 473 Table 13–8. Instruction Set Summary (Continued) Mnemonic Description RPTB Repeat block of instructions RPTS Repeat single instruction SIGI Signal, interlocked Store floating-point value STFI Store floating-point value, interlocked Store integer STII Store integer, interlocked SUBB Subtract integers with borrow SUBB3 Subtract integers with borrow (3-operand) SUBC Subtract integers conditionally...
Page 474 Instruction Set Summary Table 13–8. Instruction Set Summary (Continued) Mnemonic Description SUBI Subtract integers SUBI3 Subtract integers (3-operand) SUBRB Subtract reverse integer with borrow SUBRF Subtract reverse floating-point value SUBRI Subtract reverse integer Software interrupt TRAP cond Trap conditionally TSTB Test bit fields TSTB3 Test bit fields (3-operand)
Page 475: Parallel Instruction Set Summary
13.3 Parallel Instruction Set Summary Table 13–9 lists the ’C3x instruction set in alphabetical order. Each table entry shows the instruction mnemonic, description, and operation. Refer to Section 13.1 for a functional listing of the instructions and individual instruc- tion descriptions. Table 13–9.
Page 476 Parallel Instruction Set Summary Table 13–9. Parallel Instruction Set Summary (Continued) (a) Parallel arithmetic with store instructions (Continued) Mnemonic Description Load floating-point value Load integer LSH3 Logical shift MPYF3 Multiply floating-point value MPYI3 Multiply integer NEGF Negate floating-point value NEGI Negate integer Complement Bitwise-logical OR...
Page 477 Table 13–9. Parallel Instruction Set Summary (Continued) (a) Parallel arithmetic with store instructions (Continued) Mnemonic Description SUBF3 Subtract floating-point value SUBI3 Subtract integer XOR3 Bitwise-exclusive OR (b) Parallel load instructions Mnemonic Description Load floating-point value Load integer (c) Parallel multiply and add/subtract instructions Mnemonic Description MPYF3...
Page 478: Group Addressing Mode Instruction Encoding
Group Addressing Mode Instruction Encoding 13.4 Group Addressing Mode Instruction Encoding The six addressing types (covered in Section 6.1, Addressing Types , on page 6-2) form these four groups of addressing modes: General addressing modes (G) 3-operand addressing modes (T) Parallel addressing modes (P) Conditional-branch addressing modes (B) 13.4.1...
Page 479 Figure 13–1 shows the encoding for the general addressing modes. The notation mod n indicates the modification field that goes with the AR n field. Refer to Table 13–10 on page 13-22 for further information. Figure 13–1. Encoding for General Addressing Modes operation operation operation...
Page 480 Group Addressing Mode Instruction Encoding Table 13–10. Indirect Addressing (a) Indirect addressing with displacement Mod Field Syntax 00000 *+AR n ( disp ) 00001 *– AR n ( disp ) *++AR n ( disp ) 00010 *– – AR n ( disp ) 00011 00100 *AR n ++( disp )
Page 481 Table 13–10. Indirect Addressing (Continued) (c) Indirect addressing with index register IR1 Mod Field Syntax 10000 *+ AR n (IR1) * – AR n (IR1) 10001 10010 * ++ AR n (IR1) 10011 * – – AR n (IR1) 10100 * AR n ++ (IR1) 10101 *AR n –...
Page 482 Group Addressing Mode Instruction Encoding 13.4.2 3-Operand Addressing Modes Instructions that use the 3-operand addressing modes, such as ADDI3, LSH3, CMPF3, or XOR3, usually have this form: src 1 operation src 2 where the destination operand is signified by dst and the source operands by src 1 and src 2;...
Page 483: Parallel Addressing Modes
The following values of AR n and AR m are valid: AR n ,0 AR m ,0 The notation modm or modn indicates the modification field that goes with the AR m or AR n field, respectively. Refer to Table 13–10 on page 13-22 for further information.
Page 484 Group Addressing Mode Instruction Encoding address, bits 15–8 the src 3 address, and bits 7–0 the src 4 address. The notations mod n and mod m indicate which modification field goes with which AR n or AR m (auxiliary register) field, respectively. The following list describes the parallel addressing operands: src 1 = R n src 2 = R n...
Page 485: Conditional-Branch Addressing Modes
13.4.4 Conditional-Branch Addressing Modes Instructions using the conditional-branch addressing modes (B cond , B cond D, CALL cond , DB cond , and DB cond D) can perform a variety of conditional operations. Bits 31–27 are set to the value of 01101, indicating conditional-branch addressing mode instructions.
Page 486: Condition Codes And Flags
Condition Codes and Flags 13.5 Condition Codes and Flags The ’C3x provides 20 condition codes (00000–10100, excluding 01011) that you can place in the cond field of any of the conditional instructions, such as RETS cond or LDF cond . The conditions include signed and unsigned compari- sons, comparisons to 0, and comparisons based on the status of individual condition flags.
Page 487 Figure 13–6. Status Register PRGW status config (’C32 only) (’C32 only) Note: xx = reserved bit, read as 0 R = read, W = write Latched floating-point underflow condition flag. LUF is set whenever UF (floating-point underflow flag) is set. LUF can be cleared only by a processor reset or by modifying it in the status register (ST).
Page 488: Condition Codes And Flags
Condition Codes and Flags Table 13–12 lists the condition mnemonic, code, description, and flag for each of the 20 condition codes. Table 13–12. Condition Codes and Flags (a) Unconditional compares Condition (b) Unsigned compares Condition (c) Signed compares Condition † = logical complement (not true condition) 13-30 Code...
Page 489 Table 13–12. Condition Codes and Flags (Continued) (d) Compare to zero Condition (e) Compare to condition flags Condition NLUF † = logical complement (not true condition) Code Description 00101 Zero 00110 Not zero 01001 Positive 00111 Negative 01010 Non-negative Code Description 01010 Non-negative...
Page 490: Individual Instructions
Refer to Chapter 6 for information on memory addressing. Code examples using many of the instructions are provided in Chapter 1, Software Applications , of the TMS320C3x General- Purpose Applications User’s Guide . 13.6.1 Symbols and Abbreviations Table 13–13 lists the symbols and abbreviations used in the individual instruc-...
Page 491: Instruction Symbols
Table 13–13. Instruction Symbols Symbol src 1 src 2 src 3 src 4 dst 1 dst 2 disp cond count | x | x(man) x(exp) || op2 x AND y x OR y x XOR y x << y x >> y *++SP *SP–...
Page 492 Individual Instructions 13.6.2 Optional Assembler Syntax The assembler allows a relaxed syntax form for some instructions. These optional forms simplify the assembly language so that special-case syntax can be ignored. A list of the optional syntax forms follows. You can omit the destination register on unary arithmetic and logical oper- ations when the same register is used as a source.
Page 493 Empty expressions are not allowed for the displacement in indirect mode: *+AR0(),R0 You can precede long immediate mode operands (destination of BR and CALL) with an @ sign: BR label You can use the LDP pseudo-op to load a register (usually DP) with the eight most significant bits (MSBs) of a relocatable address: addr,REG The @ sign is optional.
Page 494: Cpu Register Syntax
Individual Instructions Use the syntax in Table 13–14 to designate CPU registers in operands. Note the alternate notation R n , 0 any CPU register. Table 13–14. CPU Register Syntax Assemblers Syntax 13-36 Alternate Register Syntax 27, which is used to designate Assigned Function Extended-precision register Extended-precision register...
Page 495 Individual Instructions 13.6.3 Individual Instruction Descriptions Each assembly language instruction for the ’C3x is described in this section in alphabetical order. The description includes the assembler syntax, operation, operands, encoding, description, cycles, status bits, mode bit, and examples. Assembly Language Instructions 13-37...
Page 496 EXAMPLE Example Instruction Syntax INST src , dst INST1 src2 , dst1 || INST2 src3 , dst2 Each instruction begins with an assembler syntax expression. You can place labels either before the command (instruction mnemonic) on the same line or on the preceding line in the first column.
Page 497 Opcode 0 0 0 INST1 INST2 Encoding examples are shown using general addressing and parallel addressing. The instruction pair for the parallel addressing example consists of INST1 and INST2. Description Instruction execution and its effect on the rest of the processor or memory con- tents is described.
Page 498 EXAMPLE Example Instruction Example INST @98AEh,R5 The sample code presented in the above format shows the effect of the code on system pointers (for example, DP or SP), registers (for example, R1 or R5), memory at specific locations, and the seven status bits. The values given for the registers include the leading 0s to show the exponent in floating-point operations.
Page 499 Syntax ABSF src , dst | src | Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 Description The absolute value of the src operand is loaded into the dst register. The src and dst operands are assumed to be floating-point numbers.
Page 500 ABSF||STF Parallel ABSF and STF Syntax ABSF src2 , dst1 Operation | src2 | src3 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3...
Page 501 Mode Bit Example Data Memory 8098AF 8098C4 Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Operation is not affected by OVM bit value. ABSF *++AR3(IR1) ,R4 R4,*–...
Page 502 ABSI Absolute Value of Integer Syntax ABSI src , dst | src | Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 0 Description The absolute value of the src operand is loaded into the dst register. The src and dst operands are assumed to be signed integers.
Page 503 Example 1 ABSI ABSI Example 2 ABSI Data memory R0,R0 Before Instruction 00 FFFF FFCB –53 *AR1,R3 Before Instruction 00 0000 0000 00 0020 0FFFFFFCB –53 Assembly Language Instructions ABSI Absolute Value of Integer After Instruction 00 0000 0035 After Instruction 00 0000 0035 00 0020 0FFFFFFCB –53...
Page 504 ABSI||STI Parallel ABSI and STI Syntax ABSI || STI Operation | src2 | src3 src2 Operands dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3...
Page 505 Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Unaffected 1 if an integer overflow occurs;...
Page 506 ADDC Add Integer With Carry Syntax ADDC Operation dst + src + C src general addressing modes (G): Operands dst any CPU register Opcode 0 0 0 0 0 Description The sum of the dst and src operands and the carry (C) flag is loaded into the dst register.
Page 507 Syntax ADDC3 src1 + src2 + C Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst any CPU register Opcode 0 0 1 0 0 Description The sum of the src1 and src2 operands and the carry (C) flag is loaded into the dst register.
Page 508 ADDC3 Add Integer With Carry, 3-Operand Example 1 ADDC3 ADDC3 Example 2 ADDC3 Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-50 *AR5++(IR0),R5,R2 R5,*AR5++(IR0),R2 Before Instruction 00 0000 0000 00 0000 0066...
Page 509 Syntax ADDF src , dst dst + src Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 The sum of the dst and src operands is loaded into the dst register. The dst and Description src operands are assumed to be floating-point numbers.
Page 510 ADDF Add Floating-Point Values Example ADDF *AR4++(IR1),R5 Before Instruction 05 7980 0000 Data memory 809800 13-52 6.23750e+01 4809800 112B 86B2800 809800 4.7031250e+02 After Instruction 09 052C 0000 5.3268750e+02 80992B 86B2800 4.7013250e+02...
Page 511 Syntax ADDF3 src1 + src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 0 0 Description The sum of the src1 and src2 operands is loaded into the dst register. The src1, src2, and dst operands are assumed to be floating-point numbers.
Page 512 ADDF3 Add Floating Point, 3-Operand Example 1 ADDF3 ADDF3 Before Instruction Example 2 ADDF3 Before Instruction 00 0000 0000 Data memory 809821h 8099F0h Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count.
Page 513 Syntax ADDF3 Operation src1 + src2 || src3 Operands src1 src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1 src3 dst2 Opcode 1 1 0 0 1 1...
Page 514 ADDF3||STF Parallel ADDF3 and STF Mode Bit Example Before Instruction Data memory 8098A5h 8098F3h Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-56 Operation is not affected by OVM bit value. ADDF3 *+AR3(IR1),R2,R5 R4,*AR2...
Page 515 Syntax ADDI src, dst dst + src Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 0 0 1 Description The sum of the dst and src operands is loaded into the the dst register. The dst and src operands are assumed to be signed integers.
Page 516 ADDI3 Add Integer, 3-Operand Syntax ADDI3 s rc 1 + src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst any CPU register Opcode 0 0 1 0 0 0 Description The sum of the src1 and src2 operands is loaded into the dst register. The src1, src2, and dst operands are assumed to be signed integers.
Page 517 Example 1 ADDI3 Example 2 ADDI3 Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. R4,R7,R5 Before Instruction 00 0000 00DC 00 0000 0010 00 0000 00A0 *–AR3(1),*AR6 –...
Page 518 ADDI3||STI Parallel ADDI3 and STI Syntax ADDI3 Operation src1 + src2 || src3 Operands src1 src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1...
Page 519 Mode Bit Example Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Operation is affected by OVM bit value. ADDI3 *AR0 – – (IR0),R5,R0 R3,*AR7 Before Instruction...
Page 520 Bitwise-Logical AND Syntax AND src, dst Operands dst AND src Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 0 0 1 Description The bitwise-logical AND between the dst and src operands is loaded into the dst register.
Page 521 Syntax AND3 src2, src1, dst src1 AND src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): Opcode 0 0 1 0 0 0 0 Description The bitwise-logical AND between the src1 and src2 operands is loaded into the destination register.
Page 522 AND3 Bitwise-Logical AND, 3-Operand Example 1 AND3 Data memory Example 2 AND3 Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-64 *AR0 –...
Page 523 Syntax AND3 src2, src1, dst1 Operation src1 AND src2 || src3 src1 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1 src3...
Page 524 AND3||STI Parallel AND3 and STI Mode Bit Example Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-66 Operation is not affected by OVM bit value. AND3 *+AR1(IR0),R4,R7 R3,*AR2...
Page 525 Syntax ANDN src , dst dst AND src Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 0 0 1 Description The bitwise-logical AND between the dst operand and the bitwise-logical com- plement ( ) of the src operand is loaded into the dst register. The dst and src operands are assumed to be unsigned integers.
Page 526 ANDN Bitwise-Logical AND With Complement Example ANDN @980Ch,R2 Data memory 13-68 Before Instruction 00 0000 0C2F 80980Ch 0A02 After Instruction 00 0000 042D 80980Ch 0A02...
Page 527 Syntax ANDN3 src2, src1, dst src1 AND src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 0 0 0 1 Description The bitwise-logical AND between the src1 operand and the bitwise-logical complement ( ) of the src2 operand is loaded into the dst register.
Page 528 ANDN3 Bitwise-Logical ANDN, 3-Operand Example 1 ANDN3 R5,R3,R7 Example 2 ANDN3 R1,*AR5++(IR0),R0 Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-70 Before Instruction 00 0000 0C2F 00 0000 0A02 00 0000 0000...
Page 529 Syntax ASH count, dst If ( count Operation dst << count Else: dst >> | count | Operands count general addressing modes (G): dst any CPU register Opcode 0 0 0 0 0 0 1 The seven LSBs of the count operand are used to generate the 2s-comple- Description ment shift count of up to 32 bits.
Page 530 Arithmetic Shift Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example 1 ASH R1,R3 Example 2 ASH @98C3h,R5 Data memory 13-72 Unaffected 1 if an integer overflow occurs; unchanged otherwise MSB of the output 1 if a 0 result is generated;...
Page 531 Syntax ASH3 count, src, dst If ( count Operation src << count Else: src >> | count | Operands count 3-operand addressing modes (T): src 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 0 0 0 1 The seven LSBs of the count operand are used to generate the 2s-comple- Description ment shift count of up to 32 bits.
Page 532 ASH3 Arithmetic Shift, 3-Operand Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example 1 ASH3 Data memory 13-74 Unaffected 1 if an integer overflow occurs; unchanged otherwise MSB of the output 1 if a 0 result is generated;...
Page 533 Example 2 ASH3 Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8.5.2 for the effects of operand ordering on the cycle count. R1,R3,R5 Before Instruction 00 FFFF FFF8 –8 00 FFFF CB00 00 0000 0000 Assembly Language Instructions ASH3 Arithmetic Shift, 3-Operand...
Page 534 ASH3||STI Parallel ASH3 and STI Syntax ASH3 count, src2, dst1 If (coun t Operation Else: || src3 Operands count register (R n 1, 0 src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1...
Page 535 Arithmetic right shift: sign of src2 If the count operand is 0, no shift is performed, and the C bit is set to 0. The count and dst operands are assumed to be signed integers. All registers are read at the beginning and loaded at the end of the execute cycle.
Page 536 ASH3||STI Parallel ASH3 and STI Example Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-78 ASH3 R1,*AR6++(IR1),R0 R5,*AR2 Before Instruction 00 0000 0000 00 0000 FFE8 –24 00 0000 0035...
Page 537 Syntax B cond src Operation If cond is true: If src is in register-addressing mode (R n , 0 If src is in PC-relative mode (label or address), displacement + PC + 1 Else, continue src conditional-branch addressing modes (B): Operands Opcode 0 1 1 0 1...
Page 538 Bcond Branch Conditionally (Standard) Example BZ R0 Note: If a BZ instruction is executed immediately following a RND instruction with a 0 operand, the branch is not performed, because the 0 flag is not set. To circumvent this problem, execute a BZUF instead of a BZ instruction. 13-80 Before Instruction 00 0003 FF00...
Page 539 Syntax B cond D src If cond is true: Operation If src is in register-addressing mode (R n , 0 If src is in PC-relative mode (label or address), displacement + PC + 3 Else, continue src conditional-branch addressing modes (B): Operands Opcode 0 1 1 0 1...
Page 540 BcondD Branch Conditionally (Delayed) Example BNZD 36 (36 = 24h) Note: Delayed branches disable interrupts until the completion of the three instruc- tions that follow the delayed branch, regardless if the branch is or is not per- formed. The following instructions cannot be used in the next three instruc- tions following a delayed branch: B cond , B cond D, BR, BRD, CALL, CALL- cond , DB cond , DB cond D, IDLE, IDLE2, RETI cond , RETS cond , RPTB, RPTS, TRAP cond .
Page 541 Syntax BR src Operation Operands src long-immediate addressing mode Opcode 0 1 1 0 0 Description BR performs a PC-relative branch that executes in four cycles, since a pipeline flush also occurs upon execution of the branch (see Section 8.2, Pipeline Con- flicts , on page 8-4).
Page 542 Branch Unconditionally (Delayed) Syntax BRD src Operation Operands src long-immediate addressing mode Opcode 0 1 1 0 0 Description BRD signifies a delayed branch that allows the three instructions after the delayed branch to be fetched before the PC is modified. The effect is a single-cycle branch.
Page 543 Syntax CALL src Operation Next PC Operands src long-immediate addressing mode Opcode 0 1 1 0 0 Description A call is performed. The next PC value is pushed onto the system stack. The src operand is loaded into the PC. The src operand is assumed to be a 24-bit unsigned-immediate operand.
Page 544 CALLcond Call Subroutine Conditionally Syntax CALL cond src If cond is true: Operation Next PC If src is in register addressing mode (R n , 0 If src is in PC-relative mode (label or address), displacement + PC + 1 Else, continue Operands src conditional-branch addressing modes (B):...
Page 545 Example CALLNZ R5 Data memory Call Subroutine Conditionally Before Instruction 00 0000 0789 0123 809835 Assembly Language Instructions CALLcond After Instruction 00 0000 0789 0789 809836 809836h 13-87...
Page 546 CMPF Compare Floating-Point Value Syntax CMPF src, dst dst – src Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 1 0 Description The src operand is subtracted from the dst operand. The result is not loaded into any register, which allows for nondestructive compares.
Page 547 Example CMPF *+AR4,R6 Data memory 8098F3h Before Instruction 07 0C80 0000 1.4050e+02 80 98F2 070C8000 1.4050e+02 Assembly Language Instructions CMPF Compare Floating-Point Value After Instruction 07 0C80 0000 1.4050e+02 80 98F2 8098F3h 070C8000 1.4050e+02 13-89...
Page 548 CMPF3 Compare Floating-Point Value, 3-Operand Syntax CMPF3 src2, src1 src1 – src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): Opcode 0 0 1 0 Description The src2 operand is subtracted from the src1 operand. The result is not loaded into any register, which allows for nondestructive compares.
Page 549 Example CMPF3 Data memory 809831h 809852h Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Compare Floating-Point Value, 3-Operand *AR2,*AR3 – – Before Instruction 80 9831 80 9852 77A7000 2.5044e+02...
Page 550 CMPI Compare Integer Syntax CMPI src, dst dst – src Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 1 0 The src operand is subtracted from the dst operand. The result is not loaded Description into any register, thus allowing for nondestructive compares.
Page 551 Syntax CMPI3 src2, src1 src1 – src2 Operation Operands src1 3-operand addressing modes (T): src 2 3-operand addressing modes (T): Opcode 0 0 1 0 0 0 1 1 1 Description The src2 operand is subtracted from the src1 operand. The result is not loaded into any register, which allows for nondestructive compares.
Page 552 CMPI3 Compare Integer, 3-Operand Example CMPI3 Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-94 R7,R4 Before Instruction 00 0000 0898 2200 1000 00 0000 03E8 After Instruction 00 0000 0898 2200...
Page 553 Syntax DB cond AR n, src AR n – 1 Operation If cond is true and AR n If src is in register addressing mode (R n , 0 If src is in PC-relative mode (label or address), displacement + PC + 1 Else, continue Operands src conditional-branch addressing modes (B):...
Page 554 DBcond Decrement and Branch Conditionally (Standard) Cycles Status Bits Mode Bit Example CMPI DBLT 13-96 Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Operation is not affected by OVM bit value. 200,R3 AR3,R2 Before Instruction 00 0000 009F 00 0000 0080 00 0012 005F After Instruction...
Page 555 Syntax DB cond D AR n , src Operation AR n – 1 If cond is true and AR n If src is in register addressing mode (R n , 0 If src is in PC-relative mode (label or address) displacement + PC + 3 Else, continue Operands...
Page 556 DBcondD Decrement and Branch Conditionally (Delayed) Cycles Status Bits Mode Bit Example CMPI DBZD 13-98 Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Operation is not affected by OVM bit value. 26h,R2 AR5, $+110h Before Instruction 00 0000 0026 00 0067 0100 After Instruction 00 0000 0026...
Page 557 Syntax FIX src, dst fix (src ) Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 0 1 Description The floating-point operand src is rounded down to the nearest integral value less than or equal to floating-point value, and the result is loaded into the dst register.
Page 558 Floating-Point-to-Integer Conversion Example 13-100 R1,R2 Before Instruction 0A 2820 0000 1.3454e+3 00 0000 0000 After Instruction 0A 2820 0000 13454e+3 00 0000 0541 1345...
Page 559 Syntax FIX src2, dst1 STI src3 , dst2 Operation fix( src2 ) || src3 src2 Operands dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3...
Page 560 FIX||STI Parallell FIX and STI Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count.
Page 561 Syntax FLOAT src, dst float (src) Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 Description The integer operand src is converted to the floating-point value equal to it; the result is loaded into the dst register.
Page 562 FLOAT Integer-to-Floating-Point Conversion Example FLOAT *++AR2(2),R5 Data memory 809802 13-104 Before Instruction 00 034C 2000 1.27578125e+01 80 9800 After Instruction 00 72E0 0000 1.74e+02 80 9802 809802...
Page 563 Syntax FLOAT src2, dst1 Operation float (src2 ) || src3 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3 dst2 Opcode 1 1 0 1 0 1...
Page 564 FLOAT||STF Parallel FLOAT and STF Example Data memory 8098CD 809933 Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-106 FLOAT *+AR2(IR0),R6 R7,*AR1 Before Instruction 00 0000 0000 03 4C20 0000 1.27578125e+01...
Page 565 Syntax IACK src Operation Perform a dummy read operation with IACK = 0. At end of dummy read, set IACK to 1. Operands src general addressing modes (G): Opcode 0 0 0 1 1 Description A dummy read operation is performed if off-chip memory is specified. IACK is set to 0, regardless of src location, a half H1 cycle after the beginning of the decode phase of the IACK instruction.
Page 566 IACK Interrupt Acknowledge Example IACK *AR5 13-108 Before Instruction IACK After Instruction IACK...
Page 567 Syntax IDLE Operation ST(GIE) Next PC Idle until interrupt. Operands None Opcode 0 0 0 0 0 Description The global-interrupt-enable bit is set, the next PC value is loaded into the PC, and the CPU idles until an unmasked interrupt is received. When the interrupt is received, the contents of the PC are pushed onto the active system stack, the interrupt vector is read, and the interrupt service routine is executed.
Page 568 IDLE2 Low-Power Idle Syntax IDLE2 Operation ST(GIE) Next PC Idle until interrupt. Operands None Opcode 0 0 0 0 0 Description The IDLE2 instruction serves the same function as IDLE, except that it re- moves the functional clock input from the internal device. This allows for ex- tremely low power mode.
Page 569 For correct device operation, the three instructions after a delayed branch should not be IDLE or IDLE2 instructions. Cycles Status Bits Mode Bit Example IDLE2 Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Operation is not affected by OVM bit value. ;...
Page 570 Load Floating-Point Exponent Syntax LDE src, dst src ( exp ) Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 Description The exponent field of the src operand is loaded into the exponent field of the dst register.
Page 571 Example LDE R0,R5 Before Instruction 02 0005 6F30 0A 056F E332 Load Floating-Point Exponent After Instruction 4.00066337e+00 02 0005 6F30 02 056F E332 1.06749648e+03 Assembly Language Instructions 4.00066337e+00 4.16990814e+00 13-113...
Page 572 Load Floating-Point Value Syntax LDF src, dst Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 Description The src operand is loaded into the dst register. The dst and src operands are assumed to be floating-point numbers.
Page 573 Syntax LDF cond src, dst Operation If cond is true: Else: dst is unchanged. Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 1 0 0 If the condition is true, the src operand is loaded into the dst register; otherwise, Description the dst register is unchanged.
Page 574 LDFcond Load Floating-Point Value Conditionally Example LDFZ 13-116 R3,R5 Before Instruction 2C FF2C D500 1.77055560e+13 5F 0000 003E 3.96140824e+28 After Instruction 1.77055560e+13 2C FF2C D500 1.77055560e+13 2C FF2C D500...
Page 575 Syntax LDFI src, dst Operation Signal interlocked operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 0 The src operand is loaded into the dst register. An interlocked operation is sig- Description naled over XF0 and XF1.
Page 576 LDFI Load Floating-Point Value, Interlocked Example LDFI *+AR2,R7 Before Instruction 00 0000 0000 Data memory 8098F2h 13-118 80 98F1 8098F2h 584C000 –6.28125e+01 After Instruction 05 84C0 0000 –6.28125e+01 80 98F1 584C000 –6.28125e+01...
Page 577 Syntax LDF src2, dst2 LDF src1, dst1 Operation src2 || src1 src1 Operands dst1 src2 dst2 This instruction’s operands have been augmented on the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 dst1 src2 dst2 Opcode...
Page 578 LDF||LDF Parallel LDF and LDF Example Before Instruction Data memory 809857h 80988Ah Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-120 – – AR1(IR0),R7 *AR7++(1),R3 00 0000 0000 00 0000 0000...
Page 579 Syntax LDF src2, dst1 STF src3, dst2 Operation src2 || src3 src2 Operands dst1 src3 dst2 This instruction’s operands have been augmented on the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3 dst2 Opcode...
Page 580 LDF||STF Parallel LDF and STF Example Data memory 8098E7h 809900h Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-122 *AR2 – – (1),R1 R3,*AR4++(IR1) Before Instruction 00 0000 0000 05 7B40 0000...
Page 581 Syntax LDI src, dst Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 1 Description The src operand is loaded into the dst register. The dst and src operands are assumed to be signed integers. An alternate form of LDI, LDP, is used to load the data-page pointer register (DP).
Page 582 Load Integer Example LDI *–AR1(IR0),R5 Data memory 13-124 Before Instruction 00 0000 03C5 After Instruction 00 0000 0026...
Page 583 Syntax LDI cond src, dst Operation If cond is true: Else: dst is unchanged. Operands src general addressing modes (G): 0 0 any CPU register 0 1 direct 1 0 indirect (disp = 0–255, IR0, IR1) 1 1 immediate dst any CPU register Opcode 0 1 0 1 Description...
Page 584 LDIcond Load Integer Conditionally Example LDIZ *ARO++,R6 Data memory Note: Auxiliary Register Arithmetic The test condition does not affect the auxiliary register arithmetic. (AR modification always occurs.) 13-126 Before Instruction 00 0000 0FE2 4,066 80 98F0 8098F0h 027C After Instruction 00 0000 0FE2 4,066 80 98F1...
Page 585 Syntax LDII src, dst Operation Signal interlocked operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 1 The src operand is loaded into the dst register. An interlocked operation is sig- Description naled over XF0 and XF1. The src and dst operands are assumed to be signed integers.
Page 586 LDII Load Integer, Interlocked Example LDII @985Fh,R3 Data memory 13-128 Before Instruction 00 0000 0000 80985Fh After Instruction 00 0000 00DC 80985Fh...
Page 587 Syntax LDI src 2 , dst2 LDI src1, dst1 Operation src2 || src1 src1 Operands dst1 src2 dst2 This instruction’s operands have been augmented on the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 dst1 src2...
Page 588 LDI||LDI Parallel LDI and LDI Example Data memory 809825h 8098C8h Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-130 LDI *–AR1(1),R7 LDI *AR7++(IR0),R1 Before Instruction 00 0000 0000 00 0000 0000 80 9826...
Page 589 Syntax LDI src2, dst1 STI src3, dst2 Operation src2 || src3 src2 Operands dst1 src3 dst2 This instruction’s operands have been augmented on the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3 dst2 Opcode...
Page 590 LDI||STI Parallel LDI and STI Example Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-132 LDI *–AR1(1),R2 STI R7,*AR5++(IR0) Before Instruction 00 0000 0000 00 0000 0035 80 98E7 80 982C...
Page 591 Syntax LDM src, dst Operation src ( man ) Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 1 Description The mantissa field of the src operand is loaded into the mantissa field of the dst register.
Page 592 Load Data-Page Pointer Syntax LDP src, DP Operation src is the 8 MSBs of the absolute 24-bit source address ( src ). Operands The “DP” in the operand is optional. Opcode 0 0 0 0 1 Description This pseudo-op is an alternate form of the LDUI instruction, except that LDP is always in the immediate addressing mode.
Page 593 Syntax LOPOWER Operation Operands None Opcode 0 0 0 1 0 Description The device continues to execute instructions, but at the reduced rate of the CLKIN frequency divided by 16 (that is, in LOPOWER mode, a ’C3x device that supports this mode with a CLKIN frequency of 32 MHz performs in the same way as a 2-MHz ’C3x device, which has an instruction-cycle time of 1000 ns).
Page 594 Logical Shift Syntax LSH count, dst If count Operation dst << count Else: dst >> | count | Operands count general addressing modes (G): dst any CPU register Opcode 0 0 0 0 1 The seven LSBs of the count operand are used to generate the 2s-comple- Description ment shift count.
Page 595 Cycles Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example 1 Example 2 LSH *–AR5(IR1),R5 Data memory Unaffected Unaffected MSB of the output 1 if a 0 output is generated; 0 otherwise Set to the value of the last bit shifted out;...
Page 596 LSH3 Logical Shift, 3-Operand Syntax LSH3 count, src, dst Operation If count src << count Else: src >> | count | src 3-operand addressing modes (T): Operands count 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 0 0 The seven LSBs of the count operand are used to generate the 2s-comple- Description ment shift count.
Page 597 Cycles Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example 1 LSH3 R4,R7,R2 Unaffected Unaffected MSB of the output 1 if a 0 output is generated; 0 otherwise Set to the value of the last bit shifted out; 0 for a shift count of 0; unaffected if dst is not R7–R0 Operation is not affected by OVM bit value.
Page 598 LSH3 Logical Shift, 3-Operand Example 2 LSH3 *–AR4(IR1),R5,R3 Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-140 Before Instruction 00 0000 0000 00 12C0 0000 80 9908 809904h...
Page 599 Syntax LSH3 c ount, src2, dst1 Operation If count src2 << count Else: src2 >> | count | || src3 Operands count register (R n 1, 0 src1 dst1 src2 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2...
Page 600 LSH3||STI Parallel LSH3 and STI Logical right shift: If the count operand is 0, no shift is performed, and the carry bit is set to 0. The count operand is assumed to be a 7-bit signed integer, and the src2 and dst1 operands are assumed to be unsigned integers.
Page 601 Example 1 LSH3 || STI Data memory R2,*++AR3(1),R0 R4,*–AR5 Before Instruction 00 0000 0000 00 0000 0018 00 0000 00DC 80 98C2 80 98A3 8098C3h 8098A2h Assembly Language Instructions LSH3||STI Parallel LSH3 and STI After Instruction 00 AC00 0000 00 0000 0018 00 0000 00DC 80 98C3 80 98A3...
Page 602 LSH3||STI Parallel LSH3 and STI Example 2 LSH3 || STI Data memory Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-144 R7,*AR2 – – (1),R2 R0,*+AR0(1) Before Instruction...
Page 603 Syntax MAXSPEED Operation H1/16 Operands None Opcode 0 0 0 1 0 Description Exits LOPOWER power-down mode (invoked by LOPOWER instruction with opcode 10800001h). The ’LC31 or ’C32 resumes full-speed operation during the read phase of the MAXSPEED instruction. Cycles Status Bits Mode Bit Example...
Page 604 MPYF Multiply Floating-Point Value Syntax MPYF src, dst Operation src general addressing modes (G): Operands dst register (R n , 0 Opcode 0 0 0 0 1 Description The product of the dst and src operands is loaded into the dst register. The src operand is assumed to be a single-precision floating-point number, and the dst operand is an extended-precision floating-point number.
Page 605 Syntax MPYF3 src2, src1, dst src1 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 0 0 The product of the src1 and src2 operands is loaded into the dst register. The Description src1 and src2 operands are assumed to be single-precision floating-point numbers, and the dst operand is an extended-precision floating-point number.
Page 606 MPYF3 Multiply Floating-Point Value, 3-Operand Example 1 MPYF3 R0,R7,R1 Example 2 MPYF3 *+AR2(IR0),R7,R2 MPYF3 R7,*+AR2(IR0),R2 Before Instruction Data memory 80992Ah Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-148 Before Instruction 6.281250e+01...
Page 607 Syntax MPYF3 srcA, srcB, dst1 ADDF3 srcC, srcD, dst2 Operation srcA || srcC + srcD srcA Operands srcB srcC srcD dst1 dst2 src1 src2 src3 src4 Parallel MPYF3 and ADDF3 srcB dst1 dst2 Any two indirect ( disp = 0, 1 IR0, IR1) Any two register (0 register ( d 1): 0 = R0...
Page 608 MPYF3||ADDF3 Parallel MPYF3 and ADDF3 This instruction’s operands have been augmented in the following devices: srcA , srcB , srcC , srcD can be one of the following combinations: dst1 dst2 src1 src2 src3 src4 Version 4.7 or earlier of TMS320 floating-point code-generation tools Version 5.0 or later 13-150 ’C31 silicon version 6.0 or greater...
Page 609 Opcode 1 0 0 0 0 0 Description A floating-point multiplication and a floating-point addition are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. If one of the parallel operations (MPYF3) reads from a register and the operation being performed in parallel (ADDF3) writes to the same reg- ister, then MPYF3 accepts the contents of the register as input before it is mo- dified by the ADDF3.
Page 610 MPYF3||ADDF3 Parallel MPYF3 and ADDF3 Example Note: Cycle Count One cycle if: src3 and src4 are in internal memory src3 is in internal memory and src4 is in external memory Two cycles if: src3 is in external memory and src4 is in internal memory src3 and src4 are in external memory For more information see Section 8.5, Clocking Memory Accesses, on page 8-24.
Page 611 Syntax MPYF3 src2, src1, dst Operation src1 || src3 src1 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1 src3 dst2 Opcode...
Page 612 MPYF3||STF Parallel MPYF3 and STF Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example Before Instruction Data memory 80982Ah 809860h Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count.
Page 613 Syntax MPYF3 srcA, srcB, dst1 SUBF3 srcC, srcD, dst2 Operation srcA || srcD – srcC srcA Operands srcB srcC srcD dst1 dst2 src1 src2 src3 src4 Parallel MPYF3 and SUBF3 srcB dst1 dst2 Any two indirect ( disp = 0, 1, IR0, IR1) Any two register (0 register ( d1 ): 0 = R0...
Page 614 MPYF3||ADDF3 Parallel MPYF3 and ADDF3 This instruction’s operands have been augmented in the following devices: srcA , srcB , srcC , srcD can be one of the following combinations: dst1 dst2 src1 src2 src3 src4 Version 4.7 or earlier of TMS320 floating-point code-generation tools Version 5.0 or later 13-156 ’C31 silicon version 6.0 or greater...
Page 615 Opcode 1 0 0 0 0 1 Description A floating-point multiplication and a floating-point subtraction are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. If one of the parallel operations (MPYF3) reads from a register and the operation being performed in parallel (SUBF3) writes to the same reg- ister, MPYF3 accepts as input the contents of the register before it is modified by the SUBF3.
Page 616 MPYF3||SUBF3 Parallel MPYF3 and SUBF3 Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example Before Instruction Data memory 80990Ch 8098B2h 13-158 1 if a floating-point underflow occurs; unchanged otherwise 1 if a floating-point overflow occurs; unchanged otherwise 1 if a floating-point underflow occurs;...
Page 617 Syntax MPYI src, dst Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 Description The product of the dst and src operands is loaded into the dst register. The src and dst operands, when read, are assumed to be 24-bit signed integers. The result is assumed to be a 48-bit signed integer.
Page 618 MPYI Multiply Integer Example MPYI R1,R5 13-160 Before Instruction 00 0033 C251 3,392,081 00 0078 B600 7,910,912 After Instruction 00 0033 C251 3,392,081 00 E21D 9600 –501,377,536...
Page 619 Syntax MPYI3 src2, src1, dst Operation src1 src1 3-operand addressing modes (T): Operands 0 0 any CPU register 0 1 indirect ( disp = 0, 1, IR0, IR1) 1 0 any CPU register 1 1 indirect ( disp = 0, 1, IR0, IR1) src2 3-operand addressing modes (T): 0 0 any CPU register 0 1 any CPU register...
Page 620 MPYI3 Multiply Integer, 3-Operand Example 1 MPYI3 *AR4,*–AR1(1),R2 Data memory 809850h 8098F2h Example 2 MPYI3 Data memory 8099F0h Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-162 Before Instruction 00 0000 0000...
Page 621 Syntax MPYI3 ADDI3 Operation srcA srcD + srcC srcA Operands srcB srcC srcD srcA , srcB , srcC , srcD can be one of the following combinations: dst1 dst2 src1 src2 src3 src4 Parallel MPYI3 and ADDI3 srcA, srcB, dst1 srcC, srcD, dst2 srcB dst1...
Page 622 MPYI3||ADDI3 Parallel MPYI3 and ADDI3 This instruction’s operands have been augmented in the following devices: srcA , srcB , srcC , srcD can be one of the following combinations: dst1 dst2 src1 src2 src3 src4 Version 4.7 or earlier of TMS320 floating-point code-generation tools Version 5.0 or later 13-164 ’C31 silicon version 6.0 or greater...
Page 623 Opcode Description An integer multiplication and an integer addition are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. This means that if one of the parallel operations (MPYI3) reads from a register and the operation being performed in parallel (ADDI3) writes to the same reg- ister, MPYI3 accepts the contents of the register as input before it is modified by the ADDI3.
Page 624 MPYl3||ADDl3 Parallel MPYl3 and ADD13 Data memory 80981Eh 80996Eh Note: Cycle Count One cycle if: src3 and src4 are in internal memory src3 is in internal memory and src4 is in external memory Two cycles if: src3 is in external memory and src4 is in internal memory src3 and src4 are in external memory For more information see Section 8.5, Clocking Memory Accesses, on page 8-24.
Page 625 Syntax MPYI3 Operation src1 src3 src1 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1 src3 dst2 Opcode Description An integer multiplication and an integer store are performed in parallel.
Page 626 MPYI3||STI Parallel MPYl3 and STI Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example Data memory 80995Bh 80982Eh Note: Cycle Count See Section 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count.
Page 627 Syntax MPYI3 srcA, srcB, dst1 SUBI3 srcC, srcD, dst2 Operation srcA || srcD – srcC srcA Operands srcB srcC srcD srcA , srcB , srcC , srcD can be one of the following combinations: dst1 dst2 src1 src2 src3 src4 Parallel MPYI3 and SUBI3 srcB dst1...
Page 628 MPYI3||SUBI3 Parallel MPYI3 and SUBI3 This instruction’s operands have been augmented in the following devices: srcA , srcB , srcC , srcD can be one of the following combinations: dst1 dst2 src1 src2 src3 src4 Version 4.7 or earlier of TMS320 floating-point code-generation tools 13-170 ’C31 silicon version 6.0 or greater ’C32 silicon version 2.0 or greater...
Page 629 Version 5.0 or later Opcode 1 0 0 0 1 1 Description An integer multiplication and an integer subtraction are performed in parallel. All registers are read at the beginning and loaded at the end of the execute cycle. If one of the parallel operations (MPYI3) reads from a register and the operation being performed in parallel (SUBI3) writes to the same register, MPYI3 accepts the contents of the register as input before it is modified by the SUBI3.
Page 630 MPYI3||SUBI3 Parallel MPYI3 and SUBI3 Data memory 8098E4h 8099FCh Note: Cycle Count One cycle if: src3 and src4 are in internal memory src3 is in internal memory and src4 is in external memory Two cycles if: src3 is in external memory and src4 is in internal memory src3 and src4 are in external memory For more information see Section 8.5, Clocking Memory Accesses, on page 8-24.
Page 631 Syntax NEGB src, dst Operation 0 – src – C Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 1 Description The difference of the 0 , src , and C operands is loaded into the dst register. The dst and src are assumed to be signed integers.
Page 632 NEGF Negate Floating-Point Value Syntax NEGF src, dst 0 – src Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 0 1 Description The difference of the 0 and src operands is loaded into the dst register. The dst and src operands are assumed to be floating-point numbers.
Page 633 Example NEGF *++AR3(2),R1 Data memory 809802h Before Instruction 05 7B40 0025 6.28125006e+01 80 9800 1.4050e+02 70C8000 Assembly Language Instructions Negate Floating-Point Value After Instruction 07 F380 0000 –1.4050e+02 80 9802 809802h 70C8000 1.4050e+02 NEGF 13-175...
Page 634 NEGF||STF Parallel NEGF and STF Syntax NEGF src2, dst1 Operation 0 – src2 src3 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3...
Page 635 Example Before Instruction 07 33C0 0000 00 0000 0000 Data memory 8098E1h 809804h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. *AR4– – (1),R7 NEGF R2,*++AR5(1) 1.79750e+02...
Page 636 NEGI Negate Integer Syntax NEGI src, dst 0 – src Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 0 1 Description The difference of the 0 and src operands is loaded into the dst register. The dst and src operands are assumed to be signed integers.
Page 637 Syntax NEGI 0 – src2 Operation src3 src2 Operands dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3 dst2 Opcode Description An integer negation and an integer store are performed in parallel.
Page 638 NEGI||STI Parallel NEGI and STI Example Data memory 80982Eh 8098A5h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-180 NEGI *–AR3,R2 R2,*AR1++ Before Instruction 00 0000 0019 80 98A5 80 982F...
Page 639 Syntax NOP src Operation No ALU or multiplier operations. AR n is modified if src is specified in indirect mode. Operands src general addressing modes (G): Opcode 0 0 0 Description If the src operand is specified in the indirect mode, the specified addressing operation is performed, and a dummy memory read occurs.
Page 640 NORM Normalize Syntax NORM src, dst norm ( src ) Operation Operands src general addressing modes (G): Opcode 0 0 0 0 1 Description The src operand is assumed to be an unnormalized floating-point number; that is, the implied bit is set equal to the sign bit. The dst is set equal to the normal- ized src operand with the implied bit removed.
Page 641 Example NORM R1,R2 Before Instruction 04 0000 3AF5 07 0C80 0000 Assembly Language Instructions Normalize After Instruction 04 0000 3AF5 F2 6BD4 0000 1.12451613e – 04 NORM 13-183...
Page 642 Bitwise-Logical Complement Syntax NOT src, dst Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 Description The bitwise-logical complement of the src operand is loaded into the dst regis- ter. The complement is formed by a logical NOT of each bit of the src operand. The dst and src operands are assumed to be unsigned integers.
Page 643 Example NOT @982Ch,R4 Data memory 80982Ch Before Instruction 00 0000 0000 80982Ch 5E2F Assembly Language Instructions Bitwise-Logical Complement After Instruction 00 FFFF A1D0 5E2F 13-185...
Page 644 NOT||STI Parallel NOT and STI Syntax Operation src2 || src3 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src2 dst1 src3 dst2 Opcode 1 1 1 0 0 1...
Page 645 Example Data memory 8099CCh 809840h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. *+AR2,R3 R7,*– – AR4 (IR1) Before Instruction 00 0000 0000 00 0000 00DC 80 99CB 80 9850 8099CCh...
Page 646 Bitwise-Logical OR Syntax OR src, dst dst OR src Operation Operands src general addressing modes (G): dst any CPU register Opcode 0 0 0 1 0 Description The bitwise-logical OR between the src and dst operands is loaded into the dst register.
Page 647 Example OR *++AR1(IR1),R2 Data memory 809804h Before Instruction 00 1256 0000 80 9800 809804h 2BCD Assembly Language Instructions Bitwise-Logical OR After Instruction 00 1256 2BCD 80 9804 2BCD 13-189...
Page 648 Bitwise-Logical OR, 3-Operand Syntax OR3 src2, src1, dst src1 OR src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 0 0 The bitwise-logical OR between the src1 and src2 operands is loaded into the Description dst register.
Page 649 Example OR3 *++AR1(IR1),R2,R7 Data memory 809804h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Before Instruction 00 1256 0000 00 0000 0000 80 9800 809804h 2BCD Assembly Language Instructions...
Page 650 OR3||STI Parallel OR3 and STI Syntax OR3 src2, src1, dst1 Operation src1 OR src2 src3 src1 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1...
Page 651 Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example Data memory 809831h 809883h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count.
Page 652 Pop Integer Syntax POP dst Operation *SP– – Operands dst register (R n , 0 Opcode 0 0 0 Description The top of the current system stack is popped and loaded into the dst register (32 LSBs). The top of the stack is assumed to be a signed integer. The POP is performed with a postdecrement of the stack pointer.
Page 653 Syntax POPF dst Operation *SP–– Operands dst register (R n , 0 Opcode 0 0 0 0 1 Description The top of the current system stack (32 MSBs) is popped and loaded into the dst register. The top of the stack is assumed to be a floating-point number. The POP is performed with a postdecrement of the stack pointer.
Page 654 PUSH PUSH Integer Syntax PUSH src Operation Operands src register (R n , 0 Opcode 0 0 0 0 1 Description The contents of the src register (32 LSBs) are pushed on the current system stack. The src is assumed to be a signed integer. The PUSH is performed with a preincrement of the stack pointer.
Page 655 Syntax PUSHF src Operation Operands src register (R n , 0 Opcode 0 0 0 0 1 Description The contents of the src register (32 MSBs) are pushed on the current system stack. The src is assumed to be a floating-point number. The PUSH is per- formed with a preincrement of the stack pointer.
Page 656 RETIcond Return From Interrupt Conditionally Syntax RETI cond If cond is true: Operation *SP – – Else, continue. Operands None Opcode 0 1 1 1 1 Description A conditional return is performed. If the condition is true, the top of the stack is popped to the PC, and a 1 is written to the global interrupt enable (GIE) bit of the status register.
Page 657 Example RETINZ Data memory 809830h Return From Interrupt Conditionally Before Instruction 0456 809830 809830h Assembly Language Instructions RETIcond After Instruction 0123 80982F 2000 13-199...
Page 658 RETScond Return From Subroutine Conditionally Syntax RETS cond If cond is true: Operation *SP– – Else, continue. Operands None Opcode 0 1 1 1 1 Description A conditional return is performed. If the condition is true, the top of the stack is popped to the PC.
Page 659 Example RETSGE Data memory 80983Ch Return From Subroutine Conditionally Before Instruction 0123 80983C 80983Ch Assembly Language Instructions RETScond After Instruction 0456 80983B 13-201...
Page 660 Round Floating-Point Value Syntax RND src, dst rnd( src ) Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 1 0 Description The result of rounding the src operand is loaded into the dst register.The src operand is rounded to the nearest single-precision floating-point value.
Page 661 Example RND R5,R2 Before Instruction Note: BZUF Instruction If a BZ instruction is executed immediately following an RND instruction with a 0 operand, the branch is not performed because the zero flag is not set. To circumvent this problem, execute a BZUF instruction instead of a BZ instruction.
Page 662 Rotate Left Syntax ROL dst dst left-rotated 1 bit Operation Operands dst register (R n , 0 Opcode 0 0 0 Description The contents of the dst operand are left rotated one bit and loaded into the dst register. This is a circular rotation, with the MSB simultaneously transferred into the carry (C) bit and the LSB.
Page 663 Syntax ROLC dst dst left-rotated one bit through carry bit Operation Operands dst register (R n , 0 Opcode 0 0 0 1 0 Description The contents of the dst operand are left rotated one bit through the carry (C) bit and loaded into the dst register.
Page 664 ROLC Rotate Left Through Carry Example 2 ROLC R3 13-206 Before Instruction 00 8000 4281 After Instruction 00 0000 8502...
Page 665 Syntax ROR dst Operation dst right-rotated one bit through carry bit Operands dst register (R n , 0 Opcode 0 0 0 1 0 Description The contents of the dst operand are right rotated one bit and loaded into the dst register.
Page 666 RORC Rotate Right Through Carry Syntax RORC dst Operation dst right-rotated one bit through carry bit Operands dst register (R n , 0 Opcode 0 0 0 1 0 Description The contents of the dst operand are right rotated one bit through the status reg- ister’s carry (C) bit.
Page 667 Syntax RPTB src Operation ST (RM) Next PC src long-immediate addressing mode Operands Opcode 0 1 1 0 0 Description RPTB allows a block of instructions to be repeated RC register + 1 times with- out any penalty for looping. This instruction activates the block repeat mode of updating the PC.
Page 668 RPTB Repeat Block Example RPTB Because the block-repeat modes modify the program counter, no other instruction can modify the program counter at the same time. The following two rules apply: Rule 1: The last instruction in the block (or the only instruction in a Rule 2: None of the last four instructions at the bottom of the block If either rule is violated, the PC will be undefined.
Page 669 Syntax RPTS src Operation ST (RM) Next PC Next PC Operands src general addressing modes (G): Opcode 0 0 0 The RPTS instruction allows you to repeat a single instruction src + 1 times Description without any penalty for looping. Fetches can also be made from the instruction register (IR), thus avoiding repeated memory access.
Page 670 RPTS Repeat Single Instruction Example RPTS AR5 Because the block-repeat modes modify the program counter, no other instruction can modify the program counter at the same time. Therefore, the repeated instruction cannot be a B cond , BR, DB cond , CALL, CALL cond , TRAP cond , RETI cond , RETS cond , IDLE, IDLE2, RPTB, or RPTS.
Page 671 Syntax SIGI Operation Signal interlocked operation. Wait for interlock acknowledge. Clear interlock. Operands None Opcode 0 0 0 Description An interlocked operation is signaled over XF0 and XF1. After the interlocked operation is acknowledged, the interlocked operation ends. SIGI ignores the external ready signals.
Page 672 Store Floating-Point Value Syntax STF src, dst Operation Operands src register (R n , 0 dst general addressing modes (G): Opcode 0 0 0 1 0 The src register is loaded into the dst memory location. The src and dst oper- Description ands are assumed to be floating-point numbers.
Page 673 Syntax STFI src, dst Operation Signal end of interlocked operation. Operands src register (R n , 0 dst general addressing modes (G): Opcode 0 0 0 Description The src register is loaded into the dst memory location. An interlocked opera- tion is signaled over pins XF0 and XF1.
Page 674 STFI Store Floating-Point Value, Interlocked Note: The STFI instruction is not interruptible because it completes when ready is signaled. See Section 7.4, Interlocked Operations, on page 7-13. 13-216...
Page 675 Syntax Operation src2 || src1 src1 Operands dst1 src2 dst2 This instruction’s operands have been augmented on the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 dst1 src2 dst2 Opcode 1 1 0 0 0 Description Two STF instructions are executed in parallel.
Page 676 STF||STF Parallel Store Floating-Point Value Example Data memory 809835h 8099D3h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-218 R4,*AR3 R3,*++AR5 Before Instruction 07 33C0 0000 1.79750e+02 1.4050e+02 07 0C80 0000...
Page 677 Syntax STI src, dst Operation Operands src register (R n , 0 dst general addressing modes (G): Opcode 0 0 0 1 0 The src register is loaded into the dst memory location. The src and dst oper- Description ands are assumed to be signed integers. Cycles Status Bits Mode Bit...
Page 678 STII Store Integer, Interlocked Syntax STII src, dst Operation Signal end of interlocked operation Operands src register (R n , 0 dst general addressing modes (G): Opcode 0 0 0 1 0 Description The src register is loaded into the dst memory location. An interlocked opera- tion is signaled over pins XF0 and XF1.
Page 679 Syntax Operation src2 || src1 Operands src1 dst1 src2 dst2 This instruction’s operands have been augmented on the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 dst1 src2 dst2 Opcode 1 1 0 0 0 0 Description Two integer stores are performed in parallel.
Page 680 STI||STI Parallel STI and STI Example Data memory 809838h 8098D3h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-222 STI R0,*++AR2(IR0) STI R5,*AR0 Before Instruction 00 0000 00DC 00 0000 0035 80 98D3...
Page 681 Syntax SUBB src, dst Operation dst – src – C src general addressing modes (G): Operands dst register (R n , 0 Opcode 0 0 0 1 0 Description The difference of the dst, src, and C operands is loaded into the dst register. The dst and src operands are assumed to be signed integers.
Page 682 SUBB3 Subtract Integer With Borrow, 3-Operand Syntax SUBB3 src2, src1, dst src1 – src2 – C Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 Description The difference among the src1 and src2 operands and the C flag is loaded into the dst register.
Page 683 Example SUBB3 R5,*AR5++(IR0),R0 Data memory 809800h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Subtract Integer With Borrow, 3-Operand Before Instruction 00 0000 0000 00 0000 00C7 80 9800 809800h...
Page 684 0, dst is left-shifted one bit and loaded into the dst register. The dst and src operands are assumed to be unsigned integers. You can use SUBC to perform a single step of a multi-bit integer division. See the TMS320C3x General Purpose Applications Guide for a detailed descrip- tion. Cycles...
Page 685 Example 1 SUBC Data memory 8098C5h Example 2 SUBC 3000,R0 @98C5h,R1 Before Instruction 1270 00 0000 04F6 8098C5h 1170 (3000 = 0BB8h) Before Instruction 2000 00 0000 07D0 Assembly Language Instructions Subtract Integer Conditionally After Instruction 00 0000 00C9 1170 After Instruction 00 0000 0FA0 4000...
Page 686 SUBF Subtract Floating-Point Value Syntax SUBF src , dst Operation dst – src src general addressing modes (G): Operands dst register (R n , 0 Opcode 0 0 0 1 0 The difference between the dst operand and the src operand is loaded into the Description dst register.
Page 687 Example SUBF Before Instruction 07 33C0 0000 Data memory 809888h *AR0 – – (IR0),R5 1.79750000e+02 80 9888 809888h 70C8000 1.4050e+02 Assembly Language Instructions SUBF Subtract Floating-Point Value After Instruction 05 1D00 0000 3.9250e+01 80 9808 70C8000 1.4050e+02 13-229...
Page 688 SUBF3 Subtract Floating-Point Value, 3-Operand Syntax SUBF3 src2, src1, dst src1 – src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 Description The difference between the src1 and src2 operands is loaded into the dst reg- ister.
Page 689 Example 1 SUBF3 Before Instruction Data memory 809888h 809851h Example 2 SUBF3 Before Instruction 03 4C20 0000 00 0000 0000 05 7B40 0000 Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count.
Page 690 SUBF3||STF Parallel SUBF3 and STF Syntax SUBF3 src1, src2, dst1 Operation src2 – src1 || src3 src1 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1...
Page 691 Example Before Instruction 00 0000 0000 05 7B40 0000 07 33C0 0000 Data memory 8098B0h 809860h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Parallel SUBF3 and STF SUBF3 R1,*–AR4(IR1),R0...
Page 692 SUBI Subtract Integer Syntax SUBI src, dst Operation dst – src src general addressing modes (G): Operands dst register (R n , 0 Opcode 0 0 0 1 1 Description The difference between the dst operand and the src operand is loaded into the dst register.
Page 693 Syntax SUBI3 src2, src1, dst src1 – src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 Description The difference between the src1 operand and the src2 operand is loaded into the dst register.
Page 694 SUBI3 Subtract Integer, 3-Operand Example 1 SUBI3 Example 2 SUBI3 *–AR2(1),R4,R3 Data memory 80985Dh Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-236 R7,R2,R0 Before Instruction 00 0000 0000 00 0000 0866...
Page 695 Syntax SUBI3 src1, src2, dst1 || STI Operation src2 – src1 || src3 src1 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1...
Page 696 SUBI3||STI Parallel SUBI3 and STI Example Data memory 80983Fh 80983Ch Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-238 SUBI3 R7,*+AR2(IR0),R1 R3,*++AR7 Before Instruction 00 0000 0000 00 0000 0035 00 0000 0014...
Page 697 Syntax SUBRB src, dst Operation src – dst – C Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 Description The difference of the src, dst , and C operands is loaded into the dst register. The dst and src operands are assumed to be signed integers.
Page 698 SUBRF Subtract Reverse Floating-Point Value Syntax SUBRF src, dst Operation src – dst Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 1 1 The difference between the src operand and the dst operand is loaded into the Description dst register.
Page 699 Syntax SUBRI src, dst Operation src – dst Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 1 1 Description The difference between the src operand and the dst operand is loaded into the dst register.
Page 700 Software Interrupt Syntax Operation Performs an emulation interrupt Operands None Opcode 0 1 1 0 0 Description The SWI instruction performs an emulator interrupt. This is a reserved instruc- tion and should not be used in normal programming. Cycles Status Bits Mode Bit 13-242 24 23...
Page 701 Syntax TRAP cond N Operation ST(GIE) If cond is true: Next PC Trap vector N Else: Set ST(GIE) to original state. Continue. Operands N (0 Opcode 0 1 1 1 0 Description Interrupts are disabled globally when 0 is written to ST(GIE). If the condition is true, the contents of the PC are pushed onto the system stack, and the PC is loaded with the contents of the specified trap vector (N).
Page 702 TRAPcond Trap Conditionally Example TRAPZ Data memory Trap V.16 13-244 Before Instruction 0123 809870 809871h After Instruction 0010 809871...
Page 703 Syntax TSTB src, dst dst AND src Operation Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 1 1 Description The bitwise-logical AND of the dst and src operands is formed, but the result is not loaded in any register.
Page 704 TSTB Test Bit Fields Example TSTB *–AR4(1),R5 Data memory 8099C4h 13-246 Before Instruction 00 0000 0898 2200 80 99C5 8099C4h 1895 After Instruction 00 0000 0898 2200 80 99C5 1895...
Page 705 Syntax TSTB3 src2, src1 src1 AND src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): Opcode 0 0 1 Description The bitwise-logical AND between the src1 and src2 operands is formed but is not loaded into any register. This allows for nondestructive compares. The src1 and src2 operands are assumed to be unsigned integers.
Page 706 TSTB3 Test Bit Fields, 3-Operand Example 1 TSTB3 Data memory 809885h 80992Dh Example 2 TSTB3 Data memory 8099F8h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. 13-248 *AR5 –...
Page 707 Syntax XOR src, dst Operation dst XOR src Operands src general addressing modes (G): dst register (R n , 0 Opcode 0 0 0 1 1 Description The bitwise-exclusive OR of the src and dst operands is loaded into the dst register.
Page 708 XOR3 Bitwise-Exclusive OR, 3-Operand Syntax XOR3 src2, src1, dst src1 XOR src2 Operation Operands src1 3-operand addressing modes (T): src2 3-operand addressing modes (T): dst register (R n , 0 Opcode 0 0 1 0 1 The bitwise-exclusive OR between the src1 and src2 operands is loaded into Description the dst register.
Page 709 Example 1 XOR3 *AR3++(IR0),R7,R4 Data memory 809800h Example 2 XOR3 Data memory 809825h Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count. Bitwise-Exclusive OR, 3-Operand Before Instruction 00 0000 0000 00 0000 FFFF...
Page 710 XOR3||STI Parallel XOR3 and STI Syntax XOR3 Operation src1 XOR src2 || src3 src1 Operands src2 dst1 src3 dst2 This instruction’s operands have been augmented in the following devices: ’C31 silicon revision 6.0 or greater ’C32 silicon revision 2.0 or greater src1 src2 dst1...
Page 711 Status Bits These condition flags are modified only if the destination register is R7 – R0. Mode Bit Example Data memory 80987Eh 8098ACh Note: Cycle Count See subsection 8.5.2, Data Loads and Stores , on page 8-24 for the effects of operand ordering on the cycle count.
Page 712: Instruction Opcodes
Appendix A Instruction Opcodes The opcode fields for all TMS320C3x instructions are shown in Table A–1. Bits in the table marked with a hyphen are defined in the individual instruction descriptions (see Chapter 13, Assembly Language Instructions ). Table A–1, along with the instruction descriptions, fully defines the instruction words.
Page 713: Tms320C3X Instruction Opcodes
Instruction Opcodes Table A–1. TMS320C3x Instruction Opcodes Instruction ABSF ABSI ADDC ADDF ADDI ANDN CMPF CMPI FLOAT IDLE IDLE2 LDFI LDII LOPOWER MAXSPEED MPYF † The opcode is the same for standard and delayed instructions.
Page 714 Table A–1. TMS320C3x Instruction Opcodes (Continued) Instruction MPYI NEGB NEGF NEGI NORM POPF PUSH PUSHF ROLC RORC RPTS STFI STII SIGI SUBB SUBC SUBF SUBI † The opcode is the same for standard and delayed instructions. Instruction Opcodes Instruction Opcodes...
Page 715 Instruction Opcodes Table A–1. TMS320C3x Instruction Opcodes (Continued) Instruction SUBRB SUBRF SUBRI TSTB IACK ADDC3 ADDF3 ADDI3 AND3 ANDN3 ASH3 CMPF3 CMPI3 LSH3 MPYF3 MPYI3 SUBB3 SUBF3 SUB13 TSTB3 XOR3 LDF cond LDI cond BR(D) CALL † The opcode is the same for standard and delayed instructions.
Page 716 Table A–1. TMS320C3x Instruction Opcodes (Continued) Instruction RPTB † B cond (D) † DBcond(D) CALL cond TRAP cond RETI cond RETS cond MPYF3||ADDF3 MPYF3||SUBF3 MPYI3||ADDI3 MPYI3||SUBI3 STF||STF STI||STI LDF||LDF LDI||LDI ABSF||STF † The opcode is the same for standard and delayed instructions.
Page 717 Instruction Opcodes Table A–1. TMS320C3x Instruction Opcodes (Continued) Instruction ABSI||STI ADDF3||STF ADDI3||STI AND3||STI ASH3||STI FIX||STI FLOAT||STF LDF||STF LDI||STI LSH3||STI MPYF3||STF MPYI3||STI NEGF||STF NEGI||STI NOT||STI OR3||STI SUBF3||STF SUBI3||STI XOR3||STI Reserved for reset, traps, and interrupts † The opcode is the same for standard and delayed instructions.
Page 718 Appendix B Appendix A TMS320C31 Boot Loader Source Code This appendix contains the source code for the ’C31 boot loader.
Page 719 TMS320C31 Boot Loader Source Code ************************************************************************ C31BOOT – TMS320C31 BOOT LOADER PROGRAM (C) COPYRIGHT TEXAS INSTRUMENTS INC., 1990 NOTE: 1. AFTER DEVICE RESET, THE PROGRAM IS SET TO WAIT FOR THE EXTERNAL INTERRUPTS. THE FUNCTION SELECTION OF THE EXTERNAL INTERRUPTS IS AS FOLLOWS: –––––––––––––––––––––––––––––––––––––––––––––––––––...
Page 720 .global check .sect reset .word int0 .word int1 .word int2 .word int3 .word xint0 .word rint0 .word .word .word tint0 .word tint1 .word dint .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word .word...
Page 721 TMS320C31 Boot Loader Source Code trap11 .word 809FEBh trap12 .word 809FECh trap13 .word 809FEDh trap14 .word 809FEEh trap15 .word 809FEFh trap16 .word 809FF0h trap17 .word 809FF1h trap18 .word 809FF2h trap19 .word 809FF3h trap20 .word 809FF4h trap21 .word 809FF5h trap22 .word 809FF6h trap23 .word 809FF7h...
Page 722 ADDI load0 CALLU load2 CALLU CMPI SUBI CALLU LDIZ SUBI ADDI .space 1 serial .space 29 loop_s RPTB sub_s TSTB TMS320C31 Boot Loader Source Code *AR1++(1) ; jump last half word from mem. word sub_h,AR3 ; half word size subroutine ;...
Page 723 TMS320C31 Boot Loader Source Code load_s end_s RETSU .space 22 loop_h RPTB sub_h load_h end_h RETSU .space 26 loop_w RPTB sub_w load_w end_w RETSU .space 14 loop_b RPTB sub_b load_b end_b RETSU .space 1 .end *+AR0(4Ch),R1 R0,R0 ; test load address flag end_s R1,*AR4++(1) ;...
Page 724 TMS320C32 Boot Loader Source Code This appendix includes a description of the ’C32 boot loader sequence of events and a listing of its source code. Topic Boot-Loader Source Code Description Boot-Loader Source Code Listing Appendix C Appendix A Page ......
Page 725 Boot-Loader Source Code Description C.1 Boot-Loader Source Code Description Figure C–1 shows the boot loader program flow chart. The boot loader pro- gram starts by initializing three registers: AR7 , SP , and IR0 . These registers hold the peripheral bus memory map register base address, the timer counter register (used as a stack), and a flag that indicates the first block, respectively.
Page 726 Figure C–1. Boot-Loader Flow Chart Interrupt flag IF Memory width: R5 Serial initialize serial global control register Memory control word read routine: AR0 Restore strobe values previously saved Start program execution Boot-Loader Source Code Description Start Initialize registers: AR7, SP, IR0 Serial boot? address: AR3...
Page 727 Boot-Loader Source Code Listing C.2 Boot-Loader Source Code Listing ********************************************************************************** * C32BOOT – TMS320C32 BOOT LOADER PROGRAM (C) COPYRIGHT TEXAS INSTRUMENTS INCORPORATED, 1994 *================================================================================* * NOTE: 1. Following device reset, the program waits for an external interrupt. The interrupt type determines the initial address from which the boot...
Page 728 that to function properly, the boot loader program always expects 32-bit data from 32-bit wide memory during the boot load operation. Valid boot EPROM widths are : 1, 2, 4, 8, 16 and 32 bits. 5. A single source block cannot cross STRB boundaries. For example, its destination cannot overlap STRB0 space and IOSTRB space.
Page 729 Boot-Loader Source Code Listing * Test for INT3 and, if set exclusively, proceed with serial boot load. Else, * load AR3 with 1000h if INT0, 810000h if INT1 900000h if INT2. Also load , * appropriate boot strobe pointer * reflect 32bit memory width. If (INT0 or INT1 or INT2) and INT3, turn on the * handshake mode.
Page 730 label4 SUBI 2,AR6 CMPI 0,AR6 strobes label5 CALLU read_m AR6,label5 *================================================================================* * Read and save IOSTRB, STRB0 & STRB1 (to be loaded at end of boot load) *================================================================================* strobes CALLU R1,*+AR7(4) CALLU R1,*+AR7(6) CALLU R1,*+AR7(8) *================================================================================ * Process block size (# of bytes, half–words, or words after STRB cntrl) *================================================================================* block CALLU...
Page 731 Boot-Loader Source Code Listing CALLU R1,R4 6Ch,R1 AR7,R1,AR4 –8,R4 R4,R3 –16,R3 3,R3 TSTB 0Ch,R1 LDIZ 3,R3 *================================================================================* * Look at R5 and choose serial or memory read for block data/program *================================================================================* CMPI 0,R5 LDIEQ read_s0,AR1 LDINE read_mb,AR1 *================================================================================* * Transfer one block of data or program *================================================================================* RPTB loop4...
Page 732 read_s0 TSTB 20h,IF read_s0 0FDFh,IF *+AR7(4Ch),R1 RETSU *–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– read_mc 3,R3 read_mb 1,BK R5,BK SUBI 1,BK R3,AR6 ADDI 1,AR6 3,AR6 R5,R0 loop3 CMPI 1,R0 exit1 –1,R0 –1,AR6 loop3 exit1 SUBI 1,AR6 0,R0 0,R1 loop1 ADDI 3,SP CALLU read_m SUBI 3,SP AND3 R6,BK,R7 R0,R7 R7,R1...
Page 733 Boot-Loader Source Code Listing 2,IOF loop6 TSTB 80h,IOF loop6 6,IOF RETSU *================================================================================* C-10 ;*; assert data acknowledge ;*; (XF0 low to host) ;*; wait for data not ready ;*; (XF1 high from host) ;*; deassert data acknowledge ;*; (XF0 high to host)
Page 734 A0–A23: External address pin s for data/program memory or I/O devices. These pins are on the primary bus. address: addressing mode: The method by which an instruction interprets its oper- ands to acquire the data it needs. ALU: Arithmetic logic unit. The part of the CPU that performs arithmetic and logic operations.
Page 735 Glossary BK: Block-size register. A 32-bit register used by the ARAU in circular ad- boot loader: An on-chip code that loads and executes programs received carry bit: A bit in the status register (ST) used by the ALU for extended arith- circular addressing: Accessing data from memory, registers, and the context save/restore: A save/restore of system status (status registers, ac- CPU: Central processing unit .
Page 736 data size: The number of bits (8, 16, or 32) used to represent a particular number. decode phase: The phase of the pipeline in which the instruction is decoded (identified). DMA coprocessor: A peripheral that transfers the contents of memory loca- tions independently of the processor (except for initialization).
Page 737 Glossary IACK: Interrupt acknowledge signal . An output signal indicating that an in- IE: See internal interrupt enable register. I/O flag (IOF) register: Controls the function (general-purpose I/O or inter- index registers: Two 32-bit registers (IR0 and IR1) that are used by the internal interrupt: A hardware interrupt caused by an on-chip peripheral.
Page 738 machine cycle: See CPU cycle . mantissa: A component of a floating-point number consisting of a fraction and a sign bit. The mantissa represents a normalized fraction whose binary point is shifted by the exponent. maskable interrupt: A hardware interrupt that can be enabled or disabled through software.
Page 739 Glossary overflow flag (OV) bit: A status bit that indicates whether or not an arithme- PC: Program counte r. A register that contains the address of the next peripheral bus: A bus that is used by the CPU to communicate to the DMA pipeline: A method of executing instructions in an assembly-line fashion.
Page 740 short floating-point format: A 16-bit representation of a floating point num- ber with a 12-bit mantissa and a 4-bit exponent. short floating-point format for external 16-bit data: A 16-bit representa- tion of a floating point number with an 8-bit mantissa and an 8-bit expo- nent.
Page 741 Glossary wait state: A period of time that the CPU must wait for external program, wait-state generator: A program that can be modified to generate a limited XA0–XA13: External address pin s for data/program memory or I/O devices. XD0–XD31: External data bus pins that transfer data between the processor zero fill: The process of filling the low- or high-order bits with 0s when load- data, or I/O memory to respond when it reads from or writes to that exter- nal memory.
Page 742 16-bit-wide configured memory, TMS320C31 11-10 2-operand instruction 13-3 2-operand instruction word 8-25 3-operand addressing modes 2-17, 13-24–13-25 3-operand instruction 13-4 add, integer 13-58 arithmetic shift 13-73 bitwise-exclusive OR 13-250 bitwise-logical ANDN 13-69 OR 13-190 compare floating-point value 13-90 integer 13-93 logical shift 13-138 multiply floating-point value 13-147...
Page 743 Index arithmetic logic unit (ALU), definition D-1 assembler syntax expression, example 13-38 assembly language, instruction set 2-operand instructions 13-3 3-operand instructions 13-4 interlocked operations instructions 13-5–13-6 load and store instructions 13-2 low-power control instructions 13-5 program control instructions 13-4–13-5 assembly language instructions 13-1–13-37 3-operand instruction floating-point value 13-53–13-54 integer with carry 13-49–13-50...
Page 744 assembly language instructions (continued) normalize (NORM) 13-182–13-183 parallel instructions ABSF and STF 13-42 ABSI and STI 13-46 ADDF3 and STF 13-55 ADDI3 and STI 13-60–13-61 AND3 and STI 13-65–13-66 ASH3 and STI 13-76–13-78 FIX and STI 13-101–13-102 FLOAT and STF 13-105–13-106 LDF and LDF 13-119–13-120 LDF and STF 13-121–13-122 LDI and LDI 13-129–13-130...
Page 745 AND 13-62 3-operand 13-63 with complement (ANDN) 13-67 complement instruction (NOT) 13-184 OR instruction 13-188 block diagram, TMS320C3x 1-3 repeat-mode control bits 7-3 nested block repeats 7-8 operation 7-3–7-4 RC register value 7-7 registers (RC, RE, RS) 7-2 restrictions 7-6–7-7 RPTB instruction 7-4–7-5...
Page 746 carry bit, definition D-2 carry flag 13-29 central processing unit. See CPU circular addressing 6-21–6-25 algorithm 6-23 buffer 6-21–6-25 definition D-2 FIR filters 6-24 operation 6-23 CLKX pins 12-22 clock mode timer interrupt 12-13 timer pulse generator 12-7–12-9 clock periods, minor 8-24 compare floating-point value instruction (CMPF) 13-88 integer instruction (CMPI) 13-92...
Page 747 Index data-rate timing operation fixed 12-36 burst mode 12-36 continuous mode 12-36 variable 12-39 burst mode 12-35 continuous mode 12-40 data-page pointer (DP) 2-10, 3-4 data-receive register (DRR) 12-28 serial port 12-28–12-29 data-transfer operation, handshake 11-20 data-transmit register (DXR) 12-28, 12-32, 12-36, 12-37 data-address generation logic, definition D-2 data-page pointer (DP), definition D-2...
Page 748 5-4–5-13 2s-complement, converting IEEE format to 5-15 addition and subtraction 5-32–5-36 examples 5-34–5-36 conversion between formats 5-12–5-13 TMS320C3x to IEEE 5-22 to IEEE standard 754, 5-14 to integer 5-41–5-42 converting integer to 5-43 determining decimal equivalent 5-9 extended-precision 5-8–5-9 normalization 5-37–5-38...
Page 749 Index global-control register DMA 12-53–12-59 serial port 12-15, 12-17–12-21 timer 12-3, 12-4–12-6 handshake 11-20 hardware interrupt, definition D-3 hit, definition D-3 hold cycles 9-37 hold everything 8-15 busy external port 8-16 conditional calls and traps 8-18 multicycle data reads 8-17 I/O flag (IOF) register 3-16 bits defined 3-16 CPU register file 3-16...
Page 750 D-4 interrupt 7-26–7-37 acknowledge, instruction (IACK) 13-107 acknowledge signal, definition D-4 considerations TMS320C30 7-44–7-47 TMS320C3x 7-41–7-43 control bits 7-32 interrupt enable register (IE) 7-32 interrupt flag register (IF) 7-32 status register (ST) 7-32 CPU/DMA interaction 7-40 definition D-4...
Page 751 Index logical shift instruction (LSH) 13-136 LOPOWER 7-51–7-52 timing 7-52 low-power control instructions 13-5 idle instruction (IDLE2) 13-110 LRU cache update 4-19 LSB, definition D-4 mantissa, definition D-5 maskable interrupt, definition D-5 MAXSPEED, timing 7-52 memory 4-2 accesses 2-operand instructions 8-25 3-operand instructions 8-25 data access 8-22 data loads and stores 8-24...
Page 752 MSB, definition D-5 MSTRB signal 9-3, 9-15 multiple processors, sharing global memory 7-13 multiplication, floating-point, examples 5-29–5-31 multiplier definition D-5 floating-point/integer 2-8 multiply floating-point value instruction (MPYF) 13-146 integer instruction (MPYI) 13-159 or CPU operation with a parallel store, instruction word format 8-29 multiprocessor counter manipulation, example 7-16...
Page 753 12-34 operation configurations 12-29–12-31 receive/transmit timer control regis- ter 12-25–12-27 receive/transmit timer counter register 12-27 receive/transmit timer period register 12-28 timing 12-31–12-34 TMS320C3x interface exam- ples 12-41–12-48 timers 12-2–12-14 global-control register 12-4–12-6 initialization/reconfiguration 12-13–12-17 interrupts 12-13 operation modes 12-10–12-12 period and counter registers 12-7 pulse generation 12-7–12-9...
Page 754 program (continued) RPTB instruction 7-4–7-5 RPTS instruction 7-5–7-6 reset operation 7-21–7-25 TMS320LC31 power management mode IDLE2 7-49–7-51 LOPOWER 7-51–7-52 memory 2-19 wait due to multicycle access 8-11 until CPU data access completes 8-10 program-counter (PC) register 2-18, 3-18 programmable bank switching 9-12–9-14 wait states 9-10–9-11, 10-15–10-16 pulse mode timer interrupt 12-13...
Page 755 Index repeat end-address (RE) register 3-17, 7-2 repeat mode, definition D-6 repeat modes 7-2–7-8 control algorithm 7-4 control bits 7-3 maximum number of repeats 7-3 nested block repeats 7-8 operation 7-3–7-4 RC register value 7-7 restrictions 7-6–7-7 RPTB instruction 7-4–7-5 RPTS instruction 7-5 repeat start-address (RS) register 3-17, 7-2 repeat-counter (RC) register 3-17, 7-2...
Page 756 serial port (continued) loading 11-11 memory mapped locations for 12-17 operation configurations 12-29–12-31 port control register FSR/DR/CLKR 12-23–12-24 FSX/DX/CLKX 12-22–12-23 receive/transmit timer control register 12-25–12-27 counter register 12-27 period register 12-28 registers 12-15, 12-47 timing 12-31–12-34 short floating-point format, definition D-7 integer format 5-2 definition D-7 unsigned integer format, definition D-7...
Page 757 TMS320C3x device differences 2-27 devices 1-2 compared 1-5 DSPs, introduction 1-1 functional block diagram 1-3 Index-16 TMS320C3x (continued) key specifications 1-3 serial port interface examples 12-41–12-48 TMS320LC31, power management mode, LOPOW- ER 7-51–7-52 transfer-counter register 12-51 trap 7-11–7-12 conditionally instruction (TRAPcond) 7-11,...

Texas Instruments TMS320C3x User Manual

Table of Contents

CPU Registers/Interrupt Latency

1 Introduction

2 Architectural Overview

6 Addressing Modes

7 Program Flow Control

8 Pipeline Operation

9 Tms320C30 and Tms320C31 External-Memory Interface

Tms320C31 Boot Loader

Tms320C32 Boot Loader

Instruction Opcodes

Quick Links

Chapters

Related Manuals for Texas Instruments TMS320C3x

Summary of Contents for Texas Instruments TMS320C3x