The Bus Master Reads A Burst Of Data From The Tms320C6202 - Texas Instruments TMS320C6201 Reference Manual

Burst Read Transfer
Figure 8–23. The Bus Master Reads a Burst of Data From the TMS320C6202
XCLKIN
XCS (input)
XCNTL (input)
XW/R (input)
XBE[3:0] (input)
XBLAST (input)
XAS (input)
XD
XRDY (output)
The timing diagram shown in Figure 8–23 can be referenced for a visual
description of the steps required to complete a burst read initiated by an
external host and throttled by the XRDY signal.
1 2 3
Wait
C6202 latches CNTL
1 = XBISA
Write
0000 = Word
Internal src/dst
The boot configuration for XBLAST and XRW: BLPOL = 0 and RWPOL = 0.
See Table 8–16 for more details.
Expansion Bus Host Port Operation
4 5 6
Ready
0 = XBD
Read
D1 D2
7 8 9
Wait
D3 D4
Expansion Bus 8-39