Tms320C6211/C6711 Block Diagram - Texas Instruments TMS320C6201 Reference Manual

Overview of TMS320C6000 Peripherals
Figure 1–2. TMS320C6211/C6711 Block Diagram
External
memory
interface
(EMIF)
Multichannel
buffered
serial port 1
(McBSP 1)
Multichannel
buffered
serial port 0
(McBSP 0)
Host port
interface
(HPI)
Power down logic
1-10
Enhanced L2 memory
DMA 4 banks
controller 64K bytes
Timer 1
DMA Controller: The DMA controller transfers data between address ranges
in the memory map without intervention by the CPU. The DMA controller has
four programmable channels and a fifth auxiliary channel.
EDMA Controller: The EDMA controller performs the same functions as the
DMA controller. The EDMA has sixteen programmable channels, as well as
a RAM space to hold multiple configurations for future transfers.
HPI: The HPI is a parallel port through which a host processor can directly ac-
cess the CPU's memory space. The host device has ease of access because
it is the master of the interface. The host and the CPU can exchange informa-
tion via internal or external memory. In addition, the host has direct access to
memory-mapped peripherals.
Expansion Bus: The expansion bus is a replacement for the HPI, as well as
an expansion of the EMIF. The expansion provides two distinct areas of
functionality, (host port and I/O port) which can co-exist in a system. The host
port of the expansion bus can operate in either asynchronous slave mode,
similar to the HPI, or in synchronous master/slave mode. This allows the
device to interface to a variety of host bus protocols. Synchronous FIFOs and
asynchronous peripheral I/O devices may interface to the expansion bus.
L1P cache
direct mapped
4K bytes
CPU
Instruction fetch
Instruction dispatch
Instruction decode
Data path 1 Data path 2
A register file B register file
L1 S1 M1 D1 D2
L1D cache
2–way set
Timer 0 associative
4K bytes
Control
registers
In–circuit
emulation
M2 S2 L2