Texas Instruments TMS320C6000 DSP Reference Manual
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Texas Instruments TMS320C6000 DSP Reference Manual

Multichannel buffered serial port (mcbsp)
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TMS320C6000 DSP Multichannel Buffered
Serial Port (McBSP)
Reference Guide
Literature Number: SPRU580E
December 2005

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Summary of Contents for Texas Instruments TMS320C6000 DSP

  • Page 1 TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide Literature Number: SPRU580E December 2005...
  • Page 2 SPRU580E – December 2005...

  • Page 3: Table Of Contents

    Contents ..........................Preface ..............Multichannel Buffered Serial Port (McBSP) ......................Features ....................... McBSP Interface ....................McBSP Interface ...................... McBSP Overview ..........Resetting the Serial Port: RRST, XRST, GRST, and RESET ..................Determining Ready Status ............ 3.2.1 Receive Ready Status: REVT, RINT, and RRDY ...........
  • Page 4 ....................Receive Operation ....................Transmit Operation ..................Maximum Frame Frequency ................... Frame Synchronization Ignore .......... 5.4.1 Frame Sync Ignore and Unexpected Frame Sync Pulses ............5.4.2 Data Packing using Frame Sync Ignore Bits ................Serial Port Exception Conditions ................5.5.1 Receive Overrun: RFULL ........
  • Page 5 List of Figures ....................McBSP Block Diagram ....................Frame and Clock Operation ..................... Clock and Frame Generation ....................Receive Data Clocking ....................Transmit Data Clocking ....................Sample Rate Generator ......CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 ......
  • Page 6 .................... 11-2 Data Transmit Register (DXR) ..................11-3 Serial Port Control Register (SPCR) ..................11-4 Receive Control Register (RCR) ..................11-5 Transmit Control Register (XCR) ................11-6 Sample Rate Generator Register (SRGR) ..................11-7 Multichannel Control Register (MCR) ................11-8 Receive Channel Enable Register (RCER) ................
  • Page 7 List of Tables ................ Enhanced Features on TMS320C6000 McBSP ..................... McBSP Interface Pins ....................Reset State of McBSP Pins ....................Receive Clock Selection ....................Transmit Clock Selection ................Receive Frame Synchronization Selection ................Transmit Frame Synchronization Selection .......... RCR/XCR Fields Controlling Elements per Frame and Bits per Element ................
  • Page 8 List of Tables SPRU580E – December 2005...

  • Page 9: Preface

    (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache. TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190) provides a brief description of the peripherals available on the TMS320C6000 digital signal processors (DSPs).
  • Page 10 Related Documentation From Texas Instruments TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234) is a download with the latest chip support libraries. Read This First SPRU580E – December 2005...

  • Page 11: Multichannel Buffered Serial Port (Mcbsp)

    (McBSP) in the digital signal processors (DSPs) of the TMS320C6000™ DSP family....................Topic Page ................... Features TMS320C6000, C6000, TMS320C62x, TMS320C67x, TMS320C64x, VelociTI, TMS320C6455, Code Composer Studio, ST-BUS are trademarks of Texas Instruments. SPI is a trademark of Motorola, Inc.. SPRU580E – December 2005 Multichannel Buffered Serial Port (McBSP)

  • Page 12: Features

    www.ti.com Features Features The McBSP provides these functions: • Full-duplex communication • Double-buffered data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit • Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices •...

  • Page 13: Mcbsp Interface

    Chapter 2 SPRU580E – December 2005 McBSP Interface The McBSP consists of a data path and a control path that connect to external devices....................Topic Page ............... McBSP Interface SPRU580E – December 2005 McBSP Interface...

  • Page 14: Mcbsp Interface

    www.ti.com McBSP Interface McBSP Interface The McBSP consists of a data path and a control path that connect to external devices. Separate pins for transmission and reception communicate data to these external devices. Four other pins communicate control information (clocking and frame synchronization). The device communicates to the McBSP using 32-bit-wide control and data registers accessible via the internal peripheral bus.

  • Page 15: Mcbsp Interface Pins

    www.ti.com McBSP Interface Either the CPU or the DMA/EDMA controller reads the received data from the data receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data written to DXR is shifted out to DX via the transmit shift register (XSR).
  • Page 16 www.ti.com McBSP Interface McBSP Interface SPRU580E – December 2005...

  • Page 17: Mcbsp Overview

    Chapter 3 SPRU580E – December 2005 McBSP Overview As shown in Figure 2-1, the receive operation is triple-buffered and the transmit operation is double-buffered. Receive data arrives on the DR and is shifted into the RSR. Once a full element (8, 12, 16, 20, 24, or 32 bits) is received, the RSR is copied to the receive buffer register (RBR) only if the RBR is not full.

  • Page 18: Resetting The Serial Port: Rrst, Xrst, Grst, And Reset

    www.ti.com Resetting the Serial Port: RRST, XRST, GRST, and RESET Resetting the Serial Port: RRST, XRST, GRST, and RESET The serial port can be reset in two ways: • Device reset (RESET pin is low) places the receiver, the transmitter, and the sample rate generator in reset.

  • Page 19: Determining Ready Status

    www.ti.com Determining Ready Status A transmit frame sync error (XSYNCERR) may occur the first time the transmitter is enabled (XRST = 1) after a device reset (Chapter Determining Ready Status The RRDY and XRDY bits in SPCR indicate the ready state of the McBSP receiver and transmitter, respectively.

  • Page 20: Frame And Clock Configuration

    www.ti.com Frame and Clock Configuration Frame and Clock Configuration Figure 3-1 shows typical operation of the McBSP clock and frame sync signals. Serial clocks CLKR and CLKX define the boundaries between bits for receive and transmit, respectively. Similarly, frame sync signals FSR and FSX define the beginning of an element and/or frame transfer.

  • Page 21: Clocks, Frames, And Data

    Chapter 4 SPRU580E – December 2005 Clocks, Frames, and Data The McBSP has several ways of selecting clocking and framing for both the receiver and transmitter. Clocking and framing can be sent to both portions by the sample rate generator. Each portion can select external clocking and/or framing independently....................

  • Page 22: Frame And Clock Operation

    www.ti.com Frame and Clock Operation Figure 4-1 is a block diagram of the clock and frame selection circuitry. Figure 4-1. Clock and Frame Generation Clock selection Frame selection FSXM CLKXM FSXP CLKXP See inset See inset See inset FSX pin CLKX pin CLKX_int FSX_int...

  • Page 23: Sample Rate Generator Clocking And Framing

    www.ti.com Sample Rate Generator Clocking and Framing On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used to shift and clock out transmit data. Data is always transmitted on the rising edge of CLKX_int. If CLKXP = 1 and external clocking is selected (CLKXM = 0 and CLKX is an input), the external falling-edge-triggered input clock on CLKX is inverted to a rising-edge-triggered clock before being sent to the transmitter.

  • Page 24: Data Clock Generation

    www.ti.com Data Clock Generation Figure 4-4. Sample Rate Generator CLKGDV FPER FWID Internal clock source Frame CLKS pulse CLKSRG CLKSP CLKG CLKSM Frame pulse detection GSYNC and clock synchronization Internal clock source: • CPU clock for C620x/C670x DSP • CPU/2 clock for C621x/C671x DSP •...

  • Page 25: Sample Rate Generator Data Bit Clock Rate: Clkgdv

    www.ti.com Data Clock Generation 4.3.2 Sample Rate Generator Data Bit Clock Rate: CLKGDV The first divider stage generates the serial data bit clock from the input clock. This divider stage uses a counter that is preloaded by CLKGDV and that contains the divide ratio value. The output of this stage is the data bit clock that is output on the sample rate generator output, CLKG, and that serves as the input for the second and third divider stages.

  • Page 26: Clkg Synchronization And Fsg Generation When Gsync = 1 And Clkgdv

    www.ti.com Data Clock Generation inactive-to-active transition on FSR triggers a resynchronization of CLKG and the generation of FSG. CLKG always begins at a high state after synchronization. Also, FSR is always detected at the same edge of CLKS that generates CLKG, regardless of the length the FSR pulse. Although an external FSR is provided, FSG can still drive internal receive frame synchronization when GSYNC = 1.

  • Page 27: Digital Loopback Mode: Dlb

    www.ti.com Data Clock Generation When GSYNC = 1, the transmitter can operate synchronously with the receiver, provided that the following conditions are met: • FSX is programmed to be driven by the sample rate generator frame sync, FSG (FSGM = 1 in SRGR and FSXM = 1 in PCR).

  • Page 28: Frame Sync Generation

    www.ti.com Frame Sync Generation device stops the serial clock between data transfers, the McBSP interprets it as a slow-down serial clock. Ensure that there are no glitches on the CLK(R/X) lines as the McBSP may interpret them as clock-edge transitions. Restarting the serial clock is equivalent to a normal clock transition after a slow CLK(R/X) cycle.

  • Page 29: Receive Frame Sync Selection: Dlb, Fsrm, Gsync

    www.ti.com Frame Sync Generation When the sample rate generator comes out of reset, FSG is in an inactive (low) state. After this, when FRST = 1 and FSGM = 1, frame sync signals are generated. The frame width value (FWID + 1) is counted down on every CLKG cycle until it reaches 0 when FSG goes low.

  • Page 30: Transmit Frame Sync Selection: Fsxm, Fsgm

    www.ti.com Data and Frames 4.4.3 Transmit Frame Sync Selection: FSXM, FSGM Table 4-4 shows how you can select the source of the transmit frame synchronization signal. The three choices are: • External frame sync input • The sample rate generator frame sync signal, FSG •...

  • Page 31: Frame Length: Rfrlen1/2, Xfrlen1/2

    www.ti.com Data and Frames Figure 4-8. Dual-Phase Frame Example Phase 1 Phase 2 Phase 2 Phase 1 Phase 2 Element 3 Element 1 ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ Element 1 ¡ ¡ ¡...

  • Page 32: Data Packing Using Frame Length And Element Length

    www.ti.com Data and Frames Table 4-7. Receive/Transmit Element Length Configuration (R/X)WDLEN1/2 Element Length (Bits) Reserved Reserved 4.5.4 Data Packing using Frame Length and Element Length The frame length and element length can be manipulated to effectively pack data. For example, consider a situation in which four 8-bit elements are transferred in a single-phase frame, as shown in Figure 4-9.

  • Page 33: Data Delay: Rdatdly, Xdatdly

    www.ti.com Data and Frames Figure 4-10. Single-Phase Frame of One 32-Bit Element Element 1 CLKR RBR to DRR copy CLKX DXR to XSR Copy 4.5.5 Data Delay: RDATDLY, XDATDLY The start of a frame is defined by the first clock cycle in which frame synchronization is active. The beginning of actual data reception or transmission with respect to the start of the frame can be delayed if required.

  • Page 34: Receive Data Justification And Sign Extension: Rjust

    www.ti.com Data and Frames Another common operation uses a data delay of 2. This configuration allows the serial port to interface to different types of T1 framing devices in which the data stream is preceded by a framing bit. During the reception of such a stream with a data delay of two bits, the framing bit appears after a 1-bit delay and data appears after a 2-bit delay).

  • Page 35: Clocking And Framing Examples

    www.ti.com Clocking and Framing Examples Clocking and Framing Examples 4.6.1 Multiphase Frame Example: AC97 Figure 4-13 shows an example of the Audio Codec '97 (AC97) standard, which uses the dual-phase frame feature. The first phase consists of a single 16-bit element. The second phase consists of 12 20-bit elements.

  • Page 36: Mcbsp To St-Bus Block Diagram

    www.ti.com Clocking and Framing Examples • CLK(R/X)M = 1: CLK(R/X)_int generated internally by the sample rate generator • GSYNC = 1: CLKG is synchronized with the external frame sync signal input on FSR. CLKG is not synchronized (it runs freely) until the frame sync signal is active. Also, FSR is regenerated internally to form a minimum pulse width.

  • Page 37: Single-Rate St-Bus Clock

    www.ti.com Clocking and Framing Examples 4.6.3 Single-Rate ST-BUS Clock The example in Figure 4-17 is the same as the ST-BUS example, except for the following items: • CLKGDV = 0: CLKS drives CLK(R/X)_int without any divide down (single-rate clock). • CLKSP = 0: The rising edge of CLKS generates internal clocks CLKG and CLK(R/X)_int. The rising edge of CLKS detects the external FSR.

  • Page 38: Double-Rate Clock

    www.ti.com Clocking and Framing Examples 4.6.4 Double-Rate Clock The example in Figure 4-18 is the same as the ST-BUS example, except for the following: • CLKSP = 0: The rising edge of CLKS generates CLKG and CLK(R/X). • CLKGDV = 1: CLKG, CLKR_int, and CLKX_int frequencies are half of the CLKS frequency. •...

  • Page 39: Mcbsp Standard Operation

    Chapter 5 SPRU580E – December 2005 McBSP Standard Operation During a serial transfer, there are typically periods of serial port inactivity between packets or transfers. The receive and transmit frame synchronization pulse occurs for every serial transfer. When the McBSP is not in the reset state and has been configured for the desired operation, a serial transfer can be initiated by programming (R/X)PHASE = 0 for a single-phase frame with the required number of elements programmed in (R/X)FRLEN1.

  • Page 40: Receive Operation

    www.ti.com Receive Operation Figure 5-1 shows a single-phase data frame of one 8-bit element. Since the transfer is configured for a 1-bit data delay, the data on the DX and DR pins are available one bit clock after FS(R/X) goes active. This figure, as well as all others in this section, use the following assumptions: •...

  • Page 41: Transmit Operation

    www.ti.com Transmit Operation Transmit Operation Once transmit frame synchronization occurs, the value in the transmit shift register (XSR) is shifted out and driven on the DX pin after the appropriate data delay as set by XDATDLY. XRDY is activated after every DXR-to-XSR copy on the following falling edge of CLKX, indicating that the data transmit register (DXR) can be written with the next data to be transmitted.

  • Page 42: Frame Synchronization Ignore

    www.ti.com Frame Synchronization Ignore Note: For (R/X)DATDLY =0, the first bit of data transmitted is asynchronous to CLKX, as shown Figure 4-11 Frame Synchronization Ignore The McBSP can be configured to ignore transmit and receive frame synchronization pulses. The (R/X)FIG bit in (R/X)CR can be cleared to 0 to recognize frame sync pulses, or it can be set to 1 to ignore frame sync pulses.

  • Page 43: Data Packing Using Frame Sync Ignore Bits

    www.ti.com Frame Synchronization Ignore Figure 5-6. Unexpected Frame Synchronization With (R/X)FIG = 1 CLK(R/X) Frame synchronization ignored FS(R/X) D(R/X) (R/X)SYNCERR (low) 5.4.2 Data Packing using Frame Sync Ignore Bits Section 4.5.4 describes one method of changing the element length and frame length to simulate 32-bit serial element transfers, thus requiring much less bus bandwidth than four 8-bit transfers require.

  • Page 44: Serial Port Exception Conditions

    www.ti.com Serial Port Exception Conditions Figure 5-8. Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 Element 1 CLKR Frame ignored Frame ignored Frame ignored RBR-to-DRR copy CLKX Frame ignored Frame ignored Frame ignored DXR-to-XSR copy Serial Port Exception Conditions There are five serial port events that can constitute a system error: •...

  • Page 45: Unexpected Receive Frame Synchronization: Rsyncerr

    www.ti.com Serial Port Exception Conditions Figure 5-9 shows the receive overrun condition. Because element A is not read before the reception of element B is complete, B is not transferred to DRR yet. Another element, C, arrives and fills RSR. DRR is finally read, but not earlier than two and one half cycles before the end of element C.

  • Page 46: Decision Tree Response To Receive Frame Synchronization Pulse

    www.ti.com Serial Port Exception Conditions • Case 3: Unexpected receive frame synchronization with RFIG = 0 (unexpected frame not ignored). This case was shown in Figure 5-5 for maximum packet frequency. Figure 5-12 shows this case during normal operation of the serial port with time intervals between packets. Unexpected frame sync pulses are detected when they occur the value in RDATDLY bit clocks before the last bit of the previous element is received on DR.

  • Page 47: Transmit With Data Overwrite

    www.ti.com Serial Port Exception Conditions 5.5.3 Transmit With Data Overwrite Figure 5-13 shows what happens if the data in DXR is overwritten before it is transmitted. Suppose you load the DXR with data C. A subsequent write to the DXR overwrites C with D before C is copied to the XSR.

  • Page 48: Unexpected Transmit Frame Synchronization: Xsyncerr

    www.ti.com Serial Port Exception Conditions Figure 5-14. Transmit Empty CLKX ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ XRDY ¡...

  • Page 49: Decision Tree Response To Transmit Frame Synchronization Pulse

    www.ti.com Serial Port Exception Conditions • Case 3: Unexpected transmit frame synchronization with XFIG = 0. The case for frame synchronization with XFIG = 0 at maximum packet frequency is shown in Figure 5-5. Figure 5-17 shows the case for normal operation of the serial port with interpacket intervals.
  • Page 50 www.ti.com Serial Port Exception Conditions McBSP Standard Operation SPRU580E – December 2005...

  • Page 51: Μ-Law/A-Law Companding Hardware Operation

    Chapter 6 SPRU580E – December 2005 µ-Law/A-Law Companding Hardware Operation Companding (compressing and expanding) hardware allows compression and expansion of data in either µ-law or A-law format. The specification for µ-law and A-law log PCM is part of the CCITT G.711 recommendation. The companding standard employed in the United States and Japan is µ-law and allows 14 bits of dynamic range.

  • Page 52: Companding Internal Data

    www.ti.com Companding Internal Data The µ-law and A-law formats encode data into 8-bit code elements. Companded data is always 8-bits-wide, so the appropriate (R/X)WDLEN1/2 must be cleared to 0, indicating an 8-bit serial data stream. If companding is enabled and either phase of the frame does not have an 8-bit element length, companding continues as if the element length is eight bits.

  • Page 53: Bit Ordering

    www.ti.com Bit Ordering • Observe the quantization effects in companding by transmitting linear data and compressing and re-expanding this data. This is useful only if both XCOMPAND and RCOMPAND enable the same companding format. Figure 6-4 shows two methods by which the McBSP can compand internal data. Data paths for these two methods are indicated by (DLB) and (non-DLB) arrows.
  • Page 54 www.ti.com Bit Ordering µ-Law/A-Law Companding Hardware Operation SPRU580E – December 2005...

  • Page 55: Mcbsp Initialization Procedure

    Chapter 7 SPRU580E – December 2005 McBSP Initialization Procedure The McBSP initialization procedure varies depending on the specific system setup. Section 7.1 provides a general initialization sequence. Section 7.2 provides an initialization sequence for the special case when the external device provides the transmit frame sync FSX (FSXM = 0).

  • Page 56: General Initialization Procedure

    www.ti.com General Initialization Procedure The transmitter and the receiver of the McBSP can operate independently from each other. Therefore, they can be placed in or taken out of reset individually by modifying only the desired bit in the registers without disrupting the other portion. The steps in the following sections discuss the initialization procedure for taking both the transmitter and the receiver out of reset.

  • Page 57: Special Case: External Device Is The Transmit Frame Master

    www.ti.com Special Case: External Device is the Transmit Frame Master 3. Wait for proper internal synchronization. If the external device provides the bit clock, wait for two CLKR or CLKX cycles. If the McBSP generates the bit clock as a clock master, wait for two CLKSRG cycles. In this case, the clock source to the sample rate generator (CLKSRG) is selected by the CLKSM bit in SRGR.
  • Page 58 www.ti.com Special Case: External Device is the Transmit Frame Master To ensure proper operation when the external device is the frame master, you must assure that DXR is already serviced with the first word when a frame sync occurs. To do so, you can keep the transmitter in reset until the first frame sync is detected.
  • Page 59 www.ti.com Special Case: External Device is the Transmit Frame Master 9. Service the McBSP: a. If CPU polling is used to service the McBSP in normal operations, it can do so upon exit from the ISR. b. If CPU interrupt is used to service the McBSP in normal operations, upon XRDY interrupt service routine is entered.
  • Page 60 www.ti.com Special Case: External Device is the Transmit Frame Master McBSP Initialization Procedure SPRU580E – December 2005...

  • Page 61: Multichannel Selection Operation

    Chapter 8 SPRU580E – December 2005 Multichannel Selection Operation The multichannel selection mode allows the McBSP to select independent channels (elements) for transmit and receive in a single-phase frame. Each frame represents a time-division multiplexed data stream. For all of the McBSP, up to 32 elements in a bit stream of up to 128 elements can be enabled at any given time.

  • Page 62: Enabling Multichannel Selection

    www.ti.com Enabling Multichannel Selection If a receive element is not enabled: • RRDY is not set to 1 upon reception of the last bit of the element. • RBR is not copied to DRR upon reception of the last bit of the element. Thus, RRDY is not set active. This feature also implies that no interrupts or synchronization events are generated for this element.

  • Page 63: Element Enabling By Subframes In Partitions A And B

    www.ti.com Enabling and Masking of Channels in Normal Multichannel Selection Mode Figure 8-1. Element Enabling by Subframes in Partitions A and B Subframe # (R/X)PABLK Partition A 0-15 32-47 64-79 96-111 0-15 elements (R/X)PBBLK Partition B ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ 16-31 48-63 80-95...

  • Page 64: Xmcm = 00B For Xmcm Operation

    www.ti.com Enabling and Masking of Channels in Normal Multichannel Selection Mode The following four figures show the activity on the McBSP pins for all of the preceding XMCM bit values with the following conditions: • (R/X)PHASE = 0: Single-phase frame for multichannel selection enabled •...

  • Page 65: Changing Element Selection

    www.ti.com Changing Element Selection Figure 8-5. XMCM = 11b, RPABLK = 00b, XPABLK = X, RCER = 1010b, XCER = 1000b for XMCM Operation FS(R/X) RRDY Read of DRR Read of DRR (E1) (E3) RBR-to-DRR copy RBR-to-DRR copy RBR-to-DRR copy (E1) (E3) (E3)
  • Page 66 www.ti.com Enhanced Multichannel Selection Mode (C64x and C645x DSPs only) enable bit (RMCME) and the enhanced transmit multichannel selection enable bit (XMCME) in MCR to 1. This mode works in conjunction with six additional enhanced receive/transmit channel enable registers in the C64x and C645x McBSP: RCERE1, RCERE2, RCERE3, XCERE1, XCERE2, and XCERE3.

  • Page 67: Dx Enabler: Dxena

    www.ti.com DX Enabler: DXENA DX Enabler: DXENA The DX enabler is only available for the C621x/C671x/C64x device. The DXENA bit in SPCR controls the high impedance enable on the DX pin. When DXENA = 1, the McBSP enables extra delay for the DX pin turn-on time.
  • Page 68 www.ti.com DX Enabler: DXENA Multichannel Selection Operation SPRU580E – December 2005...

  • Page 69: Spi Protocol: Clkstp

    Chapter 9 SPRU580E – December 2005 SPI Protocol: CLKSTP A system conforming to the SPI protocol has a master-slave configuration. The SPI protocol is a 4-wire interface composed of serial data in (master in slave out or MISO), serial data out (master out slave in or MOSI), shift clock (SCK), and an active (low) slave enable (SS) signal.

  • Page 70: Spi Configuration: Mcbsp As The Master

    www.ti.com DX Enabler: DXENA Figure 9-1. SPI Configuration: McBSP as the Master SPI compliant McBSP master slave CLKX MOSI MISO Figure 9-2. Configuration: McBSP as the Slave SPI compliant McBSP slave master CLKX MISO MOSI The clock stop mode (CLKSTP) of the McBSP provides compatibility with the SPI protocol. The McBSP supports two SPI transfer formats that are specified by the clock stop mode bits (CLKSTP) in SPCR.

  • Page 71: Spi Transfer With Clkstp = 10B

    www.ti.com DX Enabler: DXENA ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ Figure 9-3. SPI Transfer with CLKSTP = 10b ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ CLKX (CLKXP=0)/SCK ¡...

  • Page 72: Mcbsp Operation As The Spi Master

    www.ti.com McBSP Operation as the SPI Master McBSP Operation as the SPI Master When the McBSP is the SPI master , it generates the master clock CLKX and the slave enable FSX. Therefore, CLKX should be configured as an output (CLKXM = 1) and FSX should be configured as an output that can be connected to the slave enable (SS) input on the slave device (FSXM = 1).

  • Page 73: Mcbsp Initialization For Spi Mode

    www.ti.com McBSP Initialization for SPI Mode McBSP Initialization for SPI Mode The operation of the serial port during device reset, transmitter reset, and receiver reset is described in Section 3.1. For McBSP operation as a master or a slave in SPI mode , you must follow these steps for proper initialization: 1.
  • Page 74 www.ti.com McBSP Initialization for SPI Mode SPI Protocol: CLKSTP SPRU580E – December 2005...

  • Page 75: Mcbsp Pins As General-Purpose I/O

    Chapter 10 SPRU580E – December 2005 McBSP Pins as General-Purpose I/O Two conditions allow the serial port pins (CLKX, FSX, DX, CLKR, FSR, DR, and CLKS) to be used as general-purpose I/O pins rather than serial port pins: • The related portion (transmitter or receiver) of the serial port is in reset: (R/X)RST = 0 in SPCR •...
  • Page 76 www.ti.com McBSP Initialization for SPI Mode McBSP Pins as General-Purpose I/O SPRU580E – December 2005...

  • Page 77: Registers

    Chapter 11 SPRU580E – December 2005 Registers Table 11-1 lists the McBSP registers and their memory addresses for the C620x/C670x DSP, Table 11-2 lists the McBSP registers for the C621x/C671x DSP, Table 11-3 lists the McBSP registers for the C64x DSP, and Table 11-4 lists the registers for the C645x DSP.

  • Page 78: Mcbsp Registers For C621X/C671X Dsp

    www.ti.com McBSP Initialization for SPI Mode Table 11-2. McBSP Registers for C621x/C671x DSP McBSPs on Device Acronym Register Name McBSP 0 McBSP 1 Section Receive buffer register RBR0 RBR1 Receive shift register RSR0 RSR1 Transmit shift register XSR0 XSR1 (2) (3) Data receive register DRR0 DRR1...

  • Page 79: Mcbsp Registers For C64X Dsp

    www.ti.com McBSP Initialization for SPI Mode Table 11-3. McBSP Registers for C64x DSP McBSPs on Device Acronym Register Name McBSP 0 McBSP 1 McBSP 2 Section Receive buffer register RBR0 RBR1 RBR2 Receive shift register RSR0 RSR1 RSR2 Transmit shift register XSR0 XSR1 XSR2...

  • Page 80: Mcbsp Registers For The C645X Dsp

    www.ti.com McBSP Initialization for SPI Mode Table 11-4. McBSP Registers for the C645x DSP McBSPs on Device Acronym Register Name McBSP 0 McBSP 1 Section Receive buffer register RBR0 RBR1 Receive shift register RSR0 RSR1 Transmit shift register XSR0 XSR1 Data receive register DRR0 DRR1...

  • Page 81: Data Receive Register (Drr)

    www.ti.com Data Receive Register (DRR) 11.1 Data Receive Register (DRR) The data receive register (DRR) contains the value to be written to the data bus (Figure 11-1 Table 11-5). For devices with an EDMA controller, DRR is mapped to memory locations on both the EDMA bus (data port) and the peripheral bus (configuration bus).

  • Page 82: Data Transmit Register (Dxr)

    www.ti.com Data Transmit Register (DXR) 11.2 Data Transmit Register (DXR) The data transmit register (DXR) contains the value to be loaded into the data transmit shift register (XSR). Figure 11-2 shows the DXR, it is described in Table 11-6. For devices with an EDMA controller, DXR is mapped to memory locations on both the EDMA bus (data port) and the peripheral bus (configuration bus).

  • Page 83: Serial Port Control Register (Spcr)

    www.ti.com Serial Port Control Register (SPCR) 11.3 Serial Port Control Register (SPCR) The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR). The SPCR contains McBSP status control bits. The SPCR is shown in Figure 11-3 and described in Table...
  • Page 84 www.ti.com Serial Port Control Register (SPCR) Table 11-7. Serial Port Control Register (SPCR) Field Descriptions (continued) Field Value Description 21-20 XINTM 0-3h Transmit interrupt (XINT) mode bit. XINT is driven by XRDY (end-of-word) and end-of-frame in A-bis mode. XINT is generated by end-of-block or end-of-frame in multichannel operation. XINT is generated by a new frame synchronization.
  • Page 85 www.ti.com Serial Port Control Register (SPCR) Table 11-7. Serial Port Control Register (SPCR) Field Descriptions (continued) Field Value Description RINTM 0-3h Receive interrupt (RINT) mode bit. RINT is driven by RRDY (end-of-word) and end-of-frame in A-bis mode. RINT is generated by end-of-block or end-of-frame in multichannel operation. RINT is generated by a new frame synchronization.

  • Page 86: Receive Control Register (Rcr)

    www.ti.com Receive Control Register (RCR) 11.4 Receive Control Register (RCR) The receive control register (RCR) configures parameters of the receive operations. The RCR is shown in Figure 11-4 and described in Table 11-8. Figure 11-4. Receive Control Register (RCR) RPHASE RFRLEN2 RWDLEN2 RCOMPAND...
  • Page 87 www.ti.com Receive Control Register (RCR) Table 11-8. Receive Control Register (RCR) Field Descriptions (continued) Field Value Description 14-8 RFRLEN1 (RFRLEN1 + 1) specifies the receive frame length (number of words) in phase 1. 1 word in phase 1 2 words in phase 1 3 words in phase 1 128 words in phase 1 RWDLEN1...

  • Page 88: Transmit Control Register (Xcr)

    www.ti.com Transmit Control Register (XCR) 11.5 Transmit Control Register (XCR) The transmit control register (XCR) configures parameters of the transmit operations. The XCR is shown Figure 11-5 and described in Table 11-9. Figure 11-5. Transmit Control Register (XCR) XPHASE XFRLEN2 XWDLEN2 XCOMPAND XFIG...
  • Page 89 www.ti.com Transmit Control Register (XCR) Table 11-9. Transmit Control Register (XCR) Field Descriptions (continued) Field Value Description 14-8 XFRLEN1 0-7Fh (XFRLEN1 + 1) specifies the transmit frame length (number of words) in phase 1. 1 word in phase 1 2 words in phase 1 3 words in phase 1 128 words in phase 1 XWDLEN1...

  • Page 90: Sample Rate Generator Register (Srgr)

    www.ti.com Sample Rate Generator Register (SRGR) 11.6 Sample Rate Generator Register (SRGR) The sample rate generator register (SRGR) controls the operation of various features of the sample rate generator. The SRGR is shown in Figure 11-6 and described in Table 11-10.

  • Page 91: Multichannel Control Register (Mcr)

    www.ti.com Multichannel Control Register (MCR) 11.7 Multichannel Control Register (MCR) The multichannel control register (MCR) contains fields that control the multichannel selection mode. The enhanced 128-channel selection mode (selected by the RMCME and XMCME bits), which allows the McBSP to select 128 channels at any time, is only available on the C64x DSP (section Section 8.5).
  • Page 92 www.ti.com Multichannel Control Register (MCR) Table 11-11. Multichannel Control Register (MCR) Field Descriptions (continued) Field Value Description 17-16 XMCM 0-3h Transmit multichannel selection enable bit. All channels are enabled without masking (DX is always driven during transmission of data). DX is masked or driven to a high-impedance state during (a) interpacket intervals, (b) when a channel is masked regardless of whether it is enabled, or ©) when a channel is disabled.

  • Page 93: Receive Channel Enable Register (Rcer)

    www.ti.com Receive Channel Enable Register (RCER) 11.8 Receive Channel Enable Register (RCER) The receive channel enable register (RCER) is used to enable any of the 32 elements for a receive. Of the 32 elements, 16 belong to a subframe in partition A and the other 16 belong to a subframe in partition B. The RCEA and RCEB fields in RCER enable elements within the 16-channel elements in partitions A and B, respectively.

  • Page 94: Transmit Channel Enable Registers (Xcer)

    www.ti.com Transmit Channel Enable Registers (XCER) 11.9 Transmit Channel Enable Registers (XCER) The transmit channel enable register (XCER) is used to enable any of the 32 elements for a transmit. Of the 32 elements, 16 belong to a subframe in partition A and the other 16 belong to a subframe in partition B.

  • Page 95: Enhanced Receive Channel Enable Registers (Rcere0-3)

    www.ti.com Enhanced Receive Channel Enable Registers (RCERE0-3) 11.10 Enhanced Receive Channel Enable Registers (RCERE0-3) Table 11-15 shows the 128 channels in a multichannel data stream and their corresponding enable bits in RCEREn. Each McBSP has four receive channel enable registers of the format shown in Figure 11-10 (RCERE0, RCERE1, RCERE2, and RCERE3) .

  • Page 96: Rceres Used In The Receive Multichannel Selection Mode

    www.ti.com Enhanced Receive Channel Enable Registers (RCERE0-3) 11.10.1 RCEREs Used in the Receive Multichannel Selection Mode For multichannel selection operation, the assignment of channels to the RCEREs depends on whether 32 or 128 channels are individually selectable, as defined by the RMCME bit. For each of these two cases, Table 11-15 shows which block of channels is assigned to each of the RCEREs used.
  • Page 97 www.ti.com Enhanced Receive Channel Enable Registers (RCERE0-3) Table 11-15. Use of the Enhanced Receive Channel Enable Registers (continued) Block Assignments Channel Assignments Number of selectable Channel channels RCEREx Block assigned Bit in RCEREx assigned Block 5 RCE16 Channel 80 RCE17 Channel 81 RCE18 Channel 82...

  • Page 98: Enhanced Transmit Channel Enable Registers (Xcere0-3)

    www.ti.com Enhanced Transmit Channel Enable Registers (XCERE0-3) 11.11 Enhanced Transmit Channel Enable Registers (XCERE0-3) Each McBSP has four transmit channel enable registers of the form shown in Figure 11-11 (XCERE0, XCERE1, XCERE2, and XCERE3) . XCERE0 is the only register used in normal mode (up to 32 channels can be selected in Partitions A and B, RMCME = XMCME = 0 in MCR) and all the four registers are used when in enhanced mode (up to 128 channels can be selected in all Partitions, RMCME = XMCME = 1 in MCR).

  • Page 99: Use Of The Enhanced Transmit Channel Enable Registers

    www.ti.com Enhanced Transmit Channel Enable Registers (XCERE0-3) When XMCM = 11b (for symmetric transmission and reception), the transmitter uses the receive channel enable registers (RCERs) to enable channels and uses the XCERs to unmask channels for transmission. Table 11-17. Use of the Enhanced Transmit Channel Enable Registers Block Assignments Channel Assignments Number of...
  • Page 100 www.ti.com Enhanced Transmit Channel Enable Registers (XCERE0-3) Table 11-17. Use of the Enhanced Transmit Channel Enable Registers (continued) Block Assignments Channel Assignments Number of selectable Channel channels XCEREx Block assigned Bit in XCEREx assigned XCERE2 Block 4 XCE0 Channel 64 XCE1 Channel 65 XCE2...

  • Page 101: Pin Control Register (Pcr)

    www.ti.com Pin Control Register (PCR) 11.12 Pin Control Register (PCR) The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR) . The PCR is also used to configure the serial port pins as general-purpose inputs or outputs during receiver and/or transmitter reset (for more information see section Chapter 10).
  • Page 102 www.ti.com Pin Control Register (PCR) Table 11-18. Pin Control Register (PCR) Field Descriptions (continued) Field Value Description Digital loop back mode is disabled (DLB = 0 in SPCR): CLKR is an input pin and is driven by an external clock. CLKR is an output pin and is driven by the internal sample-rate generator.

  • Page 103: A Revision History

    Appendix A SPRU580E – December 2005 Revision History Table A-1 lists the changes made since the previous version of this document. Table A-1. Document Revision History Reference Additions/Modifications/Deletions Global Added C645x information. Section 5.5.4 Updated Figure 5-14 to make XEMPTY signal active low. Figure 2-1 Updated Figure...
  • Page 104 TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:...

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