9.3 Emif Registers; Global Control Register; Emif Memory-Mapped Registers - Texas Instruments TMS320C6201 Reference Manual

9.3 EMIF Registers

Table 9–2. EMIF Memory-Mapped Registers
9.3.1

Global Control Register

Figure 9–6. EMIF Global Control Register Diagram
31
15 14 13 12 11
BUS
Rsv Rsv Rsv
REQ
R,+0 RW,+0 R,+11 R, +0
† Field exists only in 'C6211/C6711
‡ Fields do not exist in 'C6211/C6711
§ Fields do not exist in 'C6202.
Control of the EMIF and the memory interfaces it supports is maintained through
memory-mapped registers within the EMIF. The memory-mapped registers are
listed in Table 9–2.
Byte Address
0180 0000h
0180 0004h
0180 0008h
0180 000Ch
0180 0010h
0180 0014h
0180 0018h
0180 001Ch
The EMIF global control register (shown in Figure 9–6 and summarized in
Table 9–3) configures parameters common to all the CE spaces.
R, +0000 0000 0000 0000 00
10 9 8 7
ARDY HOLD HOLDA NOHOLD
R, +x R, +x R, +0 RW, +0
Name
EMIF global control
EMIF CE1 space control
EMIF CE0 space control
Reserved
EMIF CE2 space control
EMIF CE3 space control
EMIF SDRAM control
EMIF SDRAM timing register
Reserved
6 5 4
‡ ‡
SDCEN SSCEN CLK1EN
RW, +1 RW, +1 RW, +1
External Memory Interface
EMIF Registers
3 2 1
§ §‡ ‡
CLK2EN SSCRT RBTR8
RW, +1 RW, +0 RW, +0
16
0
‡
MAP
R, +x
9-9