Mcbsp Registers; Tms320C6211/C6711 Data Receive And Transmit Registers (Drr/Dxr) Mapping - Texas Instruments TMS320C6201 Reference Manual

McBSP Interface Signals and Registers
Table 11–2. McBSP Registers
Hex Byte Address
McBSP 0 McBSP 1
– –
– –
– –
018C 0000 0190 0000
018C 0004 0190 0004
018C 0008 0190 0008
018C 000C 0190 000C
018C 0010 0190 0010
018C 0014 0190 0014
018C 0018 0190 0018
018C 001C 0190 001C
018C 0020 0190 0020
018C 0024 0190 0024
† The RBR, RSR, and XSR are not directly accessible via the CPU or the DMA controller.
‡ The CPU and DMA controller can only read this register; they cannot write to it.
§ Applicable only to 'C6202 and 'C6203
¶ For the TMS320C6211/C6711, the DRR is also mapped at 30000000–33FFFFFFF for McBSP 0, and at
34000000h–3FFFFFFFh for McBSP 1.
# For the TMS320C6211/C6711, the DXR is also mapped at 30000000–33FFFFFFF for McBSP 0, and at
34000000h–3FFFFFFFh for McBSP 1.
Table 11–3. TMS320C6211/C6711 Data Receive and Transmit Registers (DRR/DXR)
Mapping
11-6
§
McBSP 2 Abbreviation
– RBR
– RSR
– XSR
01A4 0000 DRR
01A4 0004 DXR
01A4 0008 SPCR
01A4 000C RCR
01A4 0010 XCR
01A4 0014 SRGR
01A4 0018 MCR
01A4 001C RCER
01A4 0020 XCER
01A4 0024 PCR
Peripheral Bus
Serial Port
McBSP 0 0x018C0000
McBSP 1 0x01900000
McBSP Register Name
Receive buffer register
Receive shift register
Transmit shift register
‡ ¶
Data receive register
#
Data transmit register
Serial port control register
Receive control register
Transmit control register
Sample rate generator register
Multichannel control register
Receive channel enable register
Transmit channel enable register
Pin control register
Accessible Via
EDMA Bus
0x30000000–0x33FFFFFF
0x34000000–0x3FFFFFFF
†
Section
11.2
11.2
11.2
11.2
11.2
11.2.1
11.2.2
11.2.2
11.5.1.1
11.6.1
11.6.3.1
11.6.3.1
11.2.1