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Texas Instruments TMS320C6201 Reference Manual

Texas Instruments TMS320C6201 Reference Manual

Tms320c6000 series peripherals

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TMS320C6000 Peripherals

Reference Guide

Literature Number: SPRU190C

April 1999

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Page 1 TMS320C6000 Peripherals Reference Guide Literature Number: SPRU190C April 1999 Printed on Recycled Paper...
Page 2 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.
Page 3: Read This First
Preface Read This First About This Manual This reference guide describes the on-chip peripherals of the TMS320C6000 digital signal processors (DSPs). Main topics are the program memory, the data memory, the direct memory access (DMA) controller, the enhanced DMA control- ler (EDMA), the host-port interface (HPI), the exansion bus, the external memory interface (EMIF), the boot configuration, the multichannel buffered serial ports (McBSPs), the timers, the interrupt selector and external interrupts, and the pow-...
Page 4 Notational Conventions / Related Documentation From Texas Instruments Registers are described throughout this book in register diagrams. Each diagram shows a rectangle divided into fields that represent the fields of the register. Each field is labeled with its name inside, its beginning and ending bit numbers above, and its properties below.
Page 5 Related Documents / Trademarks TMS320C6201, TMS320C6201B Digital Signal Processors Data Sheet (literature number SPRS051) describes the features of the TMS320C6201 and TMS320C6201B fixed-point DSPs and provides pinouts, electrical specifications, and timings for the devices. TMS320C6202 Digital Signal Processor Data Sheet (literature number...
Page 6 When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated Email: dsph@ti.com Technical Documentation Services, MS 702 P.O.
Page 7 ........Describes the program and data memory system for the TMS320C6201/C6701. This includes program memory organization,cache modes, DMA and peripheral bus operation.
Page 8 Contents TMS320C6202 Program and Data Memory ......... Describes the 6202 program memory controller.
Page 9 Contents Resource Arbitration and Priority Configuration ....... . 5 30 5.9.1 DMA Auxiliary Control Register and Priority Between Channels .
Page 10 Contents 6.16 Quick DMA (QDMA) ............6 38 6.16.1 QDMA Registers .
Page 11: Table Of Contents
........... . 9 49 9.6.1 TMS320C6201/C6202/C6701 ROM Modes ......9 52 9.6.2...
Page 12 ........... 9 61 9.8.1 TMS320C6201/C6202/C6701 Memory Request Priority ....9 61 9.8.2...
Page 13 Contents 11.5.3 Frame Sync Signal Generation ........11 61 11.5.4 Clocking Examples .
Page 14 Contents 15 Designing for JTAG Emulation ..........15 1 Describes the JTAG emulator cable.
Page 15 ......... . . 1 10 2–1 TMS320C6201/C6701 Program Memory Controller in the Block Diagram ... . . 2–2 Logical Mapping of Cache Address .
Page 16 Figures 5–1 DMA Controller Interconnect to TMS320C6201/C6202/C6701 Memory-Mapped Modules ............
Page 17 Expansion Bus Boot Configuration via Pull Up/Pull Down Resistors on XD[31:0] ..8 49 9–1 External Memory Interface in the TMS320C6201/C6202/C6701 BlockDiagram ..9–2 External Memory Interface in the TMS320C6211/C6711 BlockDiagram .
Page 18 ....... 9 18 9–14 TMS320C6201/C6202/C6701 EMIF to 16M-Bit SDRAM Interface ....9 21 9–15...
Page 19 Figures 11–12 Data Delay ..............11 30 11–13 2-Bit Data Delay Used to Discard Framing Bit .
Page 20 Figures 11–54 SPI Transfer with CLKSTP = 10b ..........11 82 11–55 SPI Transfer with CLKSTP = 11b .
Page 21 ........2–2 Data Memory Organization (TMS320C6201 Revision 2) ......
Page 22 Tables 6–1 EDMA Control Registers ............6–2 EDMA Parameter RAM Contents .
Page 23 ............9 23 9–11 TMS320C6201/C6202/C6701 Implied SDRAM Configuration by MRS Value ..9 29 9–12...
Page 24 12 10 13–1 TMS320C6201/C6202/C6701 Available Interrupts ....... . 13 3 13–2...
Page 25 Chapter 1 Introduction The TMS320C6000 (‘C6000) platform of devices consists of the first off-the- shelf digital signal processors (DSPs) to use advanced very long instruction word (VLIW) to achieve high performance through increased instruction-level parallelism. The VelociTI advanced very long instruction word (VLIW) archi- tecture uses multiple execution units operating in parallel to execute multiple instructions during a single clock cycle.
Page 26 ’C54x, ’C55x fixed-point DSPs; ’C3x and ’C4x floating-point DSPs; and ’C8x multiprocessor DSPs. Now there is a new generation of DSPs, the TMS320C6000 platform, with performance and features that are reflective of Texas Instruments’ commitment to lead the world in DSP solutions. 1.1.2 Typical Applications for the TMS320 Family Table 1-1 lists some typical applications for the TMS320 family of DSPs.
Page 27: Typical Applications For The Tms320 Dsps
TMS320 Family Overview Table 1–1. Typical Applications for the TMS320 DSPs Automotive Consumer Control Adaptive ride control Digital radios/TVs Disk drive control Antiskid brakes Educational toys Engine control Cellular telephones Music synthesizers Laser printer control Digital radios Pagers Motor control Engine control Power tools Robotics control...
Page 28 Overview of the TMS320C6000 Platform of DSPs 1.2 Overview of the TMS320C6000 Platform of DSPs With a performance of up to 2000 million instructions per second (MIPS) and an efficient C compiler, the TMS320C6000 DSPs give system architects unlim- ited possibilities to differentiate their products from others. High performance, ease of use, and affordable pricing make the TMS320C6000 platform the ideal solution for multichannel, multifunction applications, such as: Pooled modems...
Page 29 Features and Options of the TMS320C6000 Devices 1.3 Features and Options of the TMS320C6000 Devices The ’C6000 devices execute up to eight 32-bit instructions per cycle. The de- vice’s core CPU consists of 32 general-purpose registers of 32-bit-word length and eight functional units: Two multipliers Six arithmetic logic units ( ALUs) The ’C6000 generation has a complete set of optimized development tools,...
Page 30 Internal peripherals External memory accessed through the external memory interface (EMIF) TMS320C6201/C6202/C6701: The ‘C6201, ‘C6202, and ‘C6701 each have separate data and program memories. The internal program memory can be mapped into the CPU address space or operated as a program cache. A 256-bit-wide path is provided from to the CPU to allow a continuous stream of eight 32-bit instructions for maximum performance.
Page 31 Features and Options of the TMS320C6000 Devices Overview of TMS320C6000 Memory TMS320C6211/C6711: The ‘C6211/C6711 is a cache-based architecture, with separate level-one program and data caches. These cache spaces are not included in the memory map and are enabled at all times. The level-one caches are only accessible by the CPU.
Page 32: Tms320C6000 Peripherals
Power-down logic is accessed directly by the CPU. Figure 1-1 shows the peripherals in the block diagram for the TMS320C6201, ‘C6202, and ‘C6701 devices. Figure 1-2 shows a block diagram for the TMS320C6211 and ’C6711 devices.
Page 33: Tms320C6201/C6202/C6701 Block Diagram
Overview of TMS320C6000 Peripherals Figure 1–1. TMS320C6201/C6202/C6701 Block Diagram Program memory/ Internal program memory Program bus cache controller External memory interface (EMIF) Expansion bus control Instruction fetch registers Timer 0 Instruction dispatch Control registers Instruction decode In-circuit emulation Timer 1...
Page 34: Tms320C6211/C6711 Block Diagram
Overview of TMS320C6000 Peripherals Figure 1–2. TMS320C6211/C6711 Block Diagram L1P cache External direct mapped memory 4K bytes interface (EMIF) Multichannel Control Instruction fetch buffered registers Instruction dispatch serial port 1 In–circuit Enhanced L2 memory (McBSP 1) Instruction decode emulation 4 banks controller 64K bytes Data path 1...
Page 35 Overview of TMS320C6000 Peripherals EMIF: The EMIF supports a glueless interface to several external devices, in- cluding: Synchronous burst SRAM (SBSRAM) Synchronous DRAM (SDRAM) Asynchronous devices, including SRAM, ROM, and FIFOs An external shared-memory device Boot Configuration: The TMS320C62x and TMS320C67x provide a variety of boot configurations that determine what actions the DSP performs after de- vice reset to prepare for initialization.
Page 36 Overview of TMS320C6000 Peripherals Timer: The ’C6000 devices have two 32-bit general-purpose timers that are used to: Time events Count events Generate pulses Interrupt the CPU Send synchronization events to the DMA/EDMA controller Interrupt Selector: The ’C6000 peripheral set produces 14–16 interrupt sources.
Page 37: Tms320C6201/C6701
TMS320C6201/C6701 Program and Data Memory This chapter describes the program memory organization, the program memory and cache modes, and access of program memory through the DMA controller for the TMS320C6201/C6701. Topic Page Program Memory Controller ........
Page 38: Tms320C6201/C6701 Program Memory Controller In The Block Diagram
Performs CPU requests to external memory through the external memory interface (EMIF) Manages the internal program memory when it is configured as cache. Figure 2–1. TMS320C6201/C6701 Program Memory Controller in the Block Diagram ’C6201/C6701 Timers Data memory Interrupt selector...
Page 39 A subsequent read of the same address causes a cache miss, and the data is again fetched from external memory. TMS320C6201/C6701 Program and Data Memory...
Page 40: Internal Program Memory Mode Summary
Internal Program Memory Cache freeze ensures that critical program data is not overwritten in the cache. Cache bypass: When the cache is bypassed, any program read fetches data from external memory. The data is not stored in the cache memory. As in cache freeze, the cache retains its state in cache bypass.
Page 41: Logical Mapping Of Cache Address
If enabled, the cache loads the fetch packet into the corresponding frame, sets the valid bit, sets the tag to bits 25–16 of the requested address, and delivers this fetch packet to the CPU after all eight instructions are available. TMS320C6201/C6701 Program and Data Memory...
Page 42 DMA Controller Access to Program Memory 2.3 DMA Controller Access to Program Memory The DMA controller can read and write to internal program memory when the memory is configured in mapped mode. The CPU always has priority over the DMA controller for access to internal program memory regardless of the value of the PRI bit for that DMA channel.
Page 43: Tms320C6X Block Diagram
HPI control DMA control Data memory EMIF control controller Host port controller CPU core Program fetch Instruction dispatch Instruction decode Data path Data path EMIF Power down Program memory controller Boot Configuration Program memory/cache TMS320C6201/C6701 Program and Data Memory...
Page 44: Data Memory Access
Data Memory Access 2.5 Data Memory Access The data memory controller services all CPU and DMA controller data re- quests to internal data memory. Figure 2–4, Figure 2–5, and Figure 2–6 show the directions of data flow and the master (requester) and slave (resource) relationships between the modules: The CPU requests data reads and writes to: Internal data memory...
Page 45: Data Memory Organization (Tms320C6201 Revision 2)
This organization allows the two CPU data ports, A and B, to simultaneously access neighboring 16-bit data elements inside the block without a resource conflict. Table 2–2. Data Memory Organization (TMS320C6201 Revision 2) Bank 0 Bank 1...
Page 46: Data Memory Controller Interconnect To Other Banks (Tms320C6201 Revision 2)
Internal Data Memory Organization Figure 2–4. Data Memory Controller Interconnect to Other Banks (TMS320C6201 Revision 2) ’C6201 CPU Side B Side A 64 K bytes Bank 3 Bank 2 Data memory controller (DMEMC) Bank 1 Bank 0 Peripheral External memory...
Page 47: Data Memory Organization (Tms320C6201 Revision 3)
This organization also allows the two CPU data ports, A and B, to simultaneously access neighboring 16-bit data elements inside the block without a resource conflict. Table 2–3. Data Memory Organization (TMS320C6201 Revision 3) Bank 0 Bank 1...
Page 48: Data Memory Controller Interconnect To Other Banks (Tms320C6201 Revision 3)
Internal Data Memory Organization Figure 2–5. Data Memory Controller Interconnect to Other Banks (TMS320C6201 Revision 3) ’C6201 CPU Side B Side A Block 1 Block 0 (32K bytes) (32K bytes) Bank 3 Bank 3 Bank 2 Bank 2 Data memory controller...
Page 49 (Block 1) Bank 4 Bank 5 Bank 6 Bank 7 First address 80008008 80008009 8000800A 8000800B 8000800C 8000800D 8000800E 8000800F (Block 1) Last address 8000FFF8 8000FFF9 8000FFFA 8000FFFB 8000FFFC 8000FFFD 8000FFFE 8000FFFF (Block 1) TMS320C6201/C6701 Program and Data Memory 2-13...
Page 50 Internal Data Memory Organization Figure 2–6. Data Memory Controller Interconnect to Other Blocks (TMS320C6701) ’C6701CPU Side B Side A Block 1 Block 0 (32K bytes) (32K bytes) Bank 7 Bank 7 Bank 6 Bank 6 Bank 5 Bank 5 Bank 4 Bank 4 Data memory controller (DMEMC)
Page 51 CPU pipeline for one CPU clock, providing two accesses in two CPU clocks. These rules apply regardless of whether the accesses are loads or stores. TMS320C6201/C6701 Program and Data Memory 2-15...
Page 52: Conflicting Internal Memory Accesses To The Same Block
DA1. Figure 3–3 shows what access conditions cause internal memory conflicts when the CPU makes two data accesses (on DA1 and DA2). Figure 2–7. Conflicting Internal Memory Accesses to the Same Block (TMS320C6201 Revisions 2 and 3) Byte Halfword...
Page 53 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0010 0100 0110 1000 1010 1100 1110 0000 0100 1000 1100 0000 1000 Note: Conflicts shown in shaded areas. TMS320C6201/C6701 Program and Data Memory 2-17...
Page 54 Internal Data Memory Organization 2.6.6 DMA Accesses to Internal Memory The DMA controller can accesss any portion of one block of internal data memory while the CPU is simultaneously accessing any portion of another block. If both the CPU and the DMA controller are accessing the same block, and portions of both accesses are to the same 16-bit bank, the DMA operation can take place first or last, depending on the CPU/DMA priority settings.
Page 55: Register Contents After Little-Endian Or Big-Endian Data Loads
0000 0076h FFFF FF98h LDBU 0000 0076h 0000 0098h 0000 0054h FFFF FFBAh 0000 0054h 00000 0BAh LDBU Note: The contents of the word in data memory at location xxxx xx00 is BA98 7654h. TMS320C6201/C6701 Program and Data Memory 2-19...
Page 56: (Tms320C6701 Only)
Note: The contents of the doubleword in data memory at location xxxx x000 before the ST instruction executes is FEDC BA98 7654 3210h. Table 2–7. Memory Contents After Little-Endian or Big-Endian Data Stores (TMS320C6201/C6701) Big-Endian Little-Endian Instruction Address Bits (1:0)
Page 57: Peripheral Bus
XXXXXXXX XXXXXXXX Halfword XXXX???? ????XXXX Halfword ????XXXX XXXX???? Byte XX?????? ??????XX Byte ??XX???? ????XX?? Byte ????XX?? ??XX???? Byte ??????XX XX?????? Note: X indicates nybbles correctly written, ? indicates nybbles with undefined value after write TMS320C6201/C6701 Program and Data Memory 2-21...
Page 58 Peripheral Bus 2.7.2 CPU Wait States Isolated peripheral bus controller accesses from the CPU causes six CPU wait states. These wait states are inserted to allow pipeline registers to break up the paths between traversing the on-chip distances between the CPU and peripherals as well as for arbitration time.
Page 59 Chapter 3 TMS320C6202 Program and Data Memory This chapter describes the TMS320C6202 program memory and data memory controller. Program memory modes including cache operation and bootload operation are discussed. Topic Page TMS320C6202 Program Memory Controller ..... Memory Mapped Operation .
Page 60: Tms320C6201/C6701/C6202 Internal Memory Configurations
3.1 TMS320C6202 Program Memory Controller The TMS320C6202 program memory controller (PMEMC) provides all of the functionality available in the TMS320C6201 revision 3. The PMEMC operates as either a 128K byte memory or direct-mapped cache. In addition to the memory/cache, the C6202 provides 128K bytes of memory that operates as a memory-mapped block.
Page 61: Tms320C6202 Program Memory Controller Block Diagram
TMS320C6202 Program Memory Controller Figure 3–1. TMS320C6202 Program Memory Controller Block Diagram C62x CPU Program fetch Block 0 Block 1 (128K bytes) (128K bytes) 0000 0000h 0002 0000h Program memory cached or mapped controller mapped (PMEMC) 0001 FFFFh 0003 FFFFh External memory interface...
Page 62 Memory Mapped Operation 3.2 Memory Mapped Operation When the PCC field of the CPU control status register is programmed for Mapped mode, both blocks of internal program RAM are mapped into internal program space. Table 3–3 shows the address space for both blocks of RAM for the map mode selected at device reset.
Page 63: Internal Program Ram Address Mapping In Cache Mode
Cache Operation 3.3 Cache Operation When the PCC field of the CPU Control Status Register is programmed for one of the Cache modes, block 1 operates as a cache while block 0 remains mapped into internal program space. Table 3–4 shows the addresses occu- pied by the RAM that is not used for cache, for each Map Mode.
Page 64 Bootload Operation 3.4 Bootload Operation The ’C6202 bootload operates identically to the C6201 revision 3. During ROM bootload, a 64K byte block of data is transferred from the beginning of CE1 to memory at address 0. During HPI bootload, the host can read or write any in- ternal or external memory location, including the entire internal program space.
Page 65: Tms320C6202 Data Memory Controller Block Diagram
3.5 TMS320C6202 Data Memory Controller The TMS320C6202 data memory controller (DMEMC) provides all of the func- tionality available in the TMS320C6201 revision 3. The C6202 DMEMC con- tains 128K bytes of RAM organized in two blocks of four banks each. Each bank is 16 bits wide.
Page 66 Chapter 4 TMS320C6211/C6711 Two-Level Internal Memory The TMS320C6211/C6711 provides a two level memory architecture for the internal program and data busses. The first level memory for both the internal program and data bus is a 4K byte cache, designated L1P for the program cache and L1D for the data cache.
Page 67: Tms320C6211/C6711 Block Diagram
Overview 4.1 Overview Figure 4–1 illustrates how the L1P, L1D, and L2 are arranged in the TMS320C6211/C6711. Figure 4–2 illustrates the bus connections between the CPU, internal memories, and the enhanced DMA for the ’C6211, and. Figure 4–1. TMS320C6211/C6711 Block Diagram L1P cache External direct mapped...
Page 68: Tms320C6211 Internal Memory Block Diagram
Overview Figure 4–2. TMS320C6211 Internal Memory Block Diagram snoop address Cache RAM L1 program cache data 4K Bytes controller address 64K Bytes Program fetch L2 cache C62x CPU controller Data path A Data path B EDMA 32 32 32 32 address data data...
Page 69: Tms320C6711 Internal Memory Block Diagram
Overview Figure 4–3. TMS320C6711 Internal Memory Block Diagram snoop address Cache RAM L1 program cache data 4K bytes controller address 64K bytes Program fetch L2 cache C67x CPU controller Data path A Data path B EDMA 32 64 32 64 address data data...
Page 70: Internal Memory Control Register Addresses
Internal Memory Control Registers 4.2 Internal Memory Control Registers The L1P, L1D, and L2 are controlled by a set of memory configuration regis- ters. The CPU can read and write to the internal memory control registers. The EDMA (and thus the HPI) can only read these registers. Table 4–3 lists these control registers and their associated addresses.
Page 71 A cache hit returns data to the CPU in a single cycle. Unlike the TMS320C6201, the L1P only operates as a cache and cannot be memory mapped. The L1P does not support freeze or bypass modes. The only values allowed for the program cache control (PCC) field in the CPU control and sta- tus register (CSR) are 000b and 010b.
Page 72: L1P Direct Mapped Cache Diagram
L1P Description Figure 4–5. L1P Direct Mapped Cache Diagram Offset Address Address Tag RAM Cache data data Data out Data out Program data There are two methods for user-controlled invalidation of data in the L1P. Writ- ing a 1 to the IP bit of the cache configuration register (CCFG) invalidates all of the cache tags in the L1P tag RAM.
Page 73: L1P Flush Base Address Register Fields (L1Pfbar)
L1P Description The second method for invalidating the L1P requires the L1PFBAR and L1PFWC registers. This is useful for invalidating a block of data in the L1P. You must first write a word–aligned address into the L1PFBAR. This value is the starting address for the invalidation.
Page 74: L1D Address Allocation
L1D Description 4.4 L1D Description The L1D is organized as a 64 set 2–way set associative cache with a 32 byte line size. The two least significant bits of a requested address are ignored by the L1D since the smallest access size is for a word. The next bit of the address is used to address the correct word.
Page 75: Level 1 Data Cache Mode Settings
L1D Description Table 4–5. Level 1 Data Cache Mode Settings Cache Mode DCC value Description Cache enable 000b 2-way cache Cache enable 010b 2-way cache Other Reserved Any initial load of an address causes a cache miss to occur. The data is loaded and stored in the internal cache memory.
Page 76: L1D 2-Way Set Associative Cache Diagram
L1D Description Figure 4–9. L1D 2–Way Set Associative Cache Diagram. Way 1 Address Address Cache Tag RAM data Data out Data out Way 0 Address Address Cache Tag RAM data Data Data out Data out Subline Word Offset Data TMS320C6211/C6711 Two-Level Internal Memory 4-11...
Page 77: L1D Flush Base Address Register Fields (L1Dfbar)
L1D Description There are two methods for user-controlled invalidation of data in the L1D. Writ- ing a 1 to the ID bit of the cache configuration register (CCFG) invalidates all the cache tags in the L1D tag RAM. This is a write-only bit, a read of this bit returns a 0.
Page 78: Cache Configuration Register Fields (Ccfg)
L2 Description 4.5 L2 Description The L2 is accessible from both the L1P and the L1D. On a cache miss from the L1P or L1D, the request is first sent to the L2 to be serviced. How the L2 services the request depends on the selected operation mode of the L2. Table 4–6 shows the supported operation modes for the L2.
Page 79: L2 Memory Configuration
L2 Description The reset value of the L2MODE field is 000b, thus the L2 RAM is configured as 64K bytes of mapped memory at reset to support bootloading. Any L2 RAM that is configured as cache is no longer in the memory map. For example, in L2 Mode 010b, the address space from 0000 8000h to 0000 FFFFh is no longer mapped.
Page 80 L2 Description 4.5.1 L2 Interfaces The L2 Controller services requests from three different requestors – the L1P, the L1D, and the Enhanced DMA. Since the L1P only sends read requests, a single 256 bit wide data bus transfers data from the L2 to the L1P. The L1D to L2 interface consists of a 128 bit read bus from the L2 to the L1D and a 128 bit write bus from the L1D to the L2.
Page 81 L2 Description The L2 uses a least recently used (LRU) replacement strategy to replace old cached data with new data. To determine which cache lines to replace, the address for the new data is used to calculate the set which that address maps to.
Page 82: L2 Cache Data Request Flow Chart
L2 Description Figure 4–14. L2 Cache Data Request Flow Chart CPU requests data Fetch data Fetch data Is data in L2? from EDMA from L2 Determine LRU location Is valid data in LRU location? Write replaced Is replaced data from L1D data in L1D? to EDMA Write replaced...
Page 83: L2 Ce Space Allocation Register Fields
L2 Description The memory attribute registers (MARs) can be programmed to turn on caching of each of the external chip enable (CE) spaces. In this way, you can perform single word reads to external mapped devices. Without this feature any external read would always read an entire L2 line of data.
Page 84 L2 Description Figure 4–15.L2 CE Space Allocation Register Fields (Continued) MAR6 rsvd CE 1.2 R,+x RW,+0 MAR7 rsvd CE 1.3 R,+x RW,+0 MAR8 rsvd CE 2.0 R,+x RW,+0 MAR9 rsvd CE 2.1 R,+x RW,+0 MAR10 rsvd CE 2.2 R,+x RW,+0 MAR11 rsvd CE 2.3...
Page 85: Memory Attribute Register Functions
L2 Description Figure 4–15.L2 CE Space Allocation Register Fields (Continued) MAR14 rsvd CE 3.2 R,+x RW,+0 MAR15 rsvd CE 3.3 R,+x RW,+0 Table 4–7. Memory Attribute Register Functions Address Range Enabled CE Space B300 0000h – B3FF FFFFh B200 0000h – B2FF FFFFh B100 0000h –...
Page 86 L2 Description 4.5.3 L2 EDMA Service EDMA accesses are only allowed to L2 space that is configured as mapped RAM. When the EDMA makes a read request to the L2, the L2 snoops the data from the L1D and stalls the EDMA until a response is returned. If data that must be updated is returned, that data is placed in the L2 and the EDMA re- quest proceeds.
Page 87: L2 Flush Register Fields (L2Flush)
L2 Description Figure 4–16. L2 Flush Register Fields (L2FLUSH) rsvd R,+x RW,+0 Table 4–8. L2 Flush Register Fields Description Field Description Flush L2 F = 0: Normal L2 operation F = 1: All L2 lines flushed Figure 4–17. L2 Clean Register Fields (L2CLEAN) rsvd R,+x RW,+0...
Page 88: L2 Flush Word Count Register Fields (L2Fwc)
L2 Description Figure 4–19. L2 Flush Word Count Register Fields (L2FWC) rsvd L2 Flush Word Count R,+x R,+x To clean a range of address from the L2, write the word-aligned address for the start of the clean into the L2CBAR. The number of words to clean is equal to the value written into the L2CWC register.
Page 89 Chapter 5 Direct Memory Access (DMA) Controller This chapter describes the direct memory access channels and registers available for the TMS320C6201/C6202/C6701 devices. Topic Page Overview ........... . .
Page 90 Overview 5.1 Overview The direct memory access (DMA) controller transfers data between regions in the memory map without intervention by the CPU. The DMA controller al- lows movement of data to and from internal memory, internal peripherals, or external devices to occur in the background of CPU operation. The DMA con- troller has four independent programmable channels, allowing four different contexts for DMA operation.
Page 91 Overview Auxiliary channel: This channel allows the host port to make requests into the CPU’s memory space. The auxiliary channel requests may be priori- tized relative to other channels and the CPU. Split-channel operation: A single channel can be used to perform both the receive and transmit element transfers from or to a peripheral simulta- neously, effectively acting like two DMA channels.
Page 92: Dma Controller Interconnect To Tms320C6201/C6202/C6701 Memory-Mapped Modules
Overview Figure 5–1 shows the ’C6000 block diagram with the DMA-related compo- nents shaded. Figure 5–1. DMA Controller Interconnect to TMS320C6201/C6202/C6701 Memory-Mapped Modules Timers Data memory Interrupt selector Peripheral McBSPs HPI control controller DMA control Data memory EMIF control controller...
Page 93: Dma Registers
DMA Registers 5.2 DMA Registers The DMA registers configure the operation of the DMA controller. Table 5–1 and Table 5–2 show how the DMA control registers are mapped in memory. These registers include the DMA global data, count reload, index, and address registers, as well as independent control registers for each channel.
Page 94: Dma Control Registers By Address
DMA Registers Table 5–1. DMA Control Registers by Address Hex Byte Described Name Address in Section 0184 0000 DMA channel 0 primary control 5.2.1 0184 0004 DMA channel 2 primary control 5.2.1 0184 0008 DMA channel 0 secondary control 5.10 0184 000C DMA channel 2 secondary control 5.10...
Page 95: Dma Control Registers By Register Name
DMA Registers Table 5–2. DMA Control Registers by Register Name Hex Byte Described Name Address in Section DMA auxiliary control register 0184 0070 5.9.1 DMA channel 0 destination address 0184 0018 DMA channel 0 primary control 0184 0000 5.2.1 DMA channel 0 secondary control 0184 0008 5.10 DMA channel 0 source address...
Page 96: Dma Channel Primary Control Register
DMA Registers 5.2.1 DMA Channel Control Registers The DMA channel primary and secondary control registers (Figure 5–2 and Figure 5–3) contain-fields that control each DMA channel independently. These fields are summarized in Table 5–3 and Table 5–4. Figure 5–2. DMA Channel Primary Control Register 19 18 DST RELOAD SRC RELOAD...
Page 97 DMA Registers Table 5–3. DMA Channel Primary Control Register Field Descriptions (Continued) Field Description Section Selects the DMA global data register to use as a programmable index 5.7.2 INDEX INDEX = 0: use DMA global index register A INDEX = 1: use DMA global index register B CNT RELOAD Transfer counter reload for autoinitialization and multiframe transfers 5.4.1.1...
Page 98: Dma Channel Secondary Control Register
DMA Registers Figure 5–3. DMA Channel Secondary Control Register Reserved DMAC EN R, +0000 0000 0000 0 RW, +000 WSYNC WSYNC RSYNC RSYNC WDROP WDROP RDROP RDROP BLOCK BLOCK LAST LAST FRAME FRAME STAT STAT COND COND COND COND COND COND Table 5–4.
Page 99: Tms320C6202 Secondary Control Register
DMA Registers The DMA channel secondary control register of the ‘C6202 has been expand- ed to include three new fields: WSPOL, RSPOL, and FSIG. This field is used to add control to a frame-synchronized data transfer. The ‘C6202 secondary control register is shown in Figure 5–4; the new field is shown in gray. Table 5–5 describes the possible configurations of the new field.
Page 100: Memory Map
Memory Map 5.3 Memory Map The DMA controller assumes the device memory map shown in Chapter 10, Boot Configuration, Reset, and Memory Maps . Requests are sent to one of five re- sources: Expansion bus External memory interface Internal program memory Internal peripheral bus Internal data memory The source address is assumed to point to one of these four spaces throughout...
Page 101 Initiating a Block Transfer 5.4 Initiating a Block Transfer Each DMA channel can be started independently, either manually through direct CPU access or automatically through autoinitialization. Each DMA channel can be stopped or paused independently through direct CPU access. The status of a DMA channel can be observed by reading the STATUS field in the DMA channel’s primary control register.
Page 102 Initiating a Block Transfer Repetitive operation: This operation is a special case of continuous opera- tion. Once a block transfer finishes, the DMA controller repeats the previous block transfer. In this case, the CPU does not preload the reload registers with new values for each block transfer.
Page 103 Initiating a Block Transfer You can rewrite the DMA channel transfer counter reload only after the next-to- last frame in the current block transfer it completed. Otherwise, the new reload values would affect subsequent frame boundaries in the current block transfer. However, if the frame size is the same for the current and next block transfers, this restriction is not relevant.
Page 104: Dma Global Count Reload Register Used As Transfer Counter Reload
Transfer Counting 5.5 Transfer Counting The DMA channel transfer counter register, shown in Figure 5–5 contains fields that represent the number of frames and the number of elements per frame to be transferred. Figure 5–6 shows the DMA global count reload regis- ter.
Page 105: Synchronization Events
Synchronization: Triggering DMA Transfers 5.6 Synchronization: Triggering DMA Transfers Synchronization allows DMA transfers to be triggered by events such as inter- rupts from internal peripherals or external pins. Three types of synchronization can be enabled for each channel: Read synchronization: Each read transfer waits for the selected event to occur before proceeding.
Page 106 Synchronization: Triggering DMA Transfers Table 5–6. Synchronization Events (Continued) Event Number Event Acronym Event Description (Binary) 01010 DMA_INT2 DMA channel 2 interrupt 01011 DMA_INT3 DMA channel 3 interrupt 01100 XEVT0 McBSP 0 transmit event 01101 REVT0 McBSP 0 receive event 01110 XEVT1 McBSP 1 transmit event...
Page 107 Synchronization: Triggering DMA Transfers 5.6.2 Automated Event Clearing The latched STAT for each synchronizing event is automatically cleared only when any action associated with that event is completed. Events are cleared as quickly as possible to reduce the minimum time between synchronizing events.
Page 108: Synchronization Flags
Synchronization: Triggering DMA Transfers Figure 5–7 shows the scenario to produce the desired synchronizing event. The figure illustrates both active-high and active-low operation, but the following explanation pertains to active-low operation. 1) The transition of EXT_INTx from high-to-low while a burst is not in prog- ress triggers a synchronizing event.
Page 109 Synchronization: Triggering DMA Transfers Another feature of this is that if the synchronization event stays active through- out a burst, then it will be latched again following the burst. This, too, was done for a more robust FIFO interface. This is due to the fact that the transition from active to inactive of the FLAG can only occur during a burst.
Page 110: Dma Channel Source Address Register
Address Generation 5.7 Address Generation For each channel, the DMA controller performs address computation for each read transfer and write transfer. The DMA controller allows creation of a variety of data structures. For example, the DMA controller can traverse an array incre- menting through every nth element.
Page 111: Dma Global Index Register
Address Generation 5.7.2 Address Adjustment With the Global Index Registers The particular DMA global index register shown in Figure 5–10 is selected via the INDEX field in the DMA channel primary control register. Unlike basic address adjustment, this mode allows different adjustment amounts depend- ing on whether the element transfer is the last in the current frame.
Page 112 Address Generation In the case of word transfers, these registers must contain values that are multi- ples of 4 and thus aligned on a word address. In the case of halfword transfers, the values must be multiples of 2 and thus aligned on a halfword address. If un- aligned values are loaded, operation is undefined.
Page 113 Address Generation 5.7.4 Using a Frame Index to Reload Addresses In an autoinitialized, single-frame block transfer, the FRAME INDEX can be used in place of a reload register to recompute the next address. If the follow- ing fields contain the values listed, a single frame transfer moves the ten bytes from a static external address to alternating locations (skipping one byte be- tween each two bytes): SRC DIR = 00b, the static source address...
Page 114: Sorting Example In Order Of Dma Transfers
Address Generation 5.7.6 Sorting The following procedure is used to locate transfers in memory by ordinal loca- tion within a frame (i.e., the first transfer of the first frame followed by the first transfer of the second frame): ELEMENT INDEX is set to F FRAME INDEX is set to –(((E –...
Page 115: Sorting In Order Of First By Address
Address Generation Table 5–8. Sorting in Order of First by Address Address (Hex) Frame Element 8000 0000 8000 0002 8000 0004 8000 0006 8000 0008 8000 000A 8000 000C 8000 000E 8000 0010 8000 0012 8000 0014 8000 0016 Direct Memory Access (DMA) Controller 5-27...
Page 116 Split-Channel Operation 5.8 Split-Channel Operation Split-channel operation allows a single DMA channel to service both the input (receive) and output (transmit) streams from an external or internal peripheral with a fixed address. 5.8.1 Split DMA Operation Split-channel operation consists of transmit element transfers and receive ele- ment transfers.
Page 117: Dma Global Address Register Used For Split Address
Split-Channel Operation The above sequence is maintained for all transfers. However, the transmit transfers do not have to wait for all previous receive element transfers to finish before proceeding. Therefore, it is possible for the transmit stream to get ahead of the receive stream. The DMA channel transfer counter decrements (or reinitialize) after the associated transmit transfer finishes.
Page 118 Resource Arbitration and Priority Configuration 5.9 Resource Arbitration and Priority Configuration Priority decides which of competing requesters have control of a resource with multiple requests. The requesters include: The DMA channels The CPU’s program and data accesses The resources include: Internal data memory Internal program memory The internal peripheral registers, which are accessed through the peripher-...
Page 119: Dma Auxiliary Control Register
Resource Arbitration and Priority Configuration Figure 5–12. DMA Auxiliary Control Register Reserved AUXPRI CH PRI R, +0 RW, +0 RW, +0 Table 5–9. DMA Auxiliary Control Register Field Descriptions Field Description CH PRI DMA channel priority CH PRI = 0000b: fixed channel priority mode auxiliary channel highest priority CH PRI = 0001b: fixed channel priority mode auxiliary channel 2nd-highest priority CH PRI = 0010b: fixed channel priority mode auxiliary channel 3rd-highest priority CH PRI = 0011b: fixed channel priority mode auxiliary channel 4th-highest priority...
Page 120 Resource Arbitration and Priority Configuration The arbitration between the DMA controller and the CPU is performed by the resource for which they are contending. For more information, see resource- specific documentation. Note that a channel’s PRI field should be modified only when that channel is paused or stopped.
Page 121: Generation Of Dma Interrupt For Channel X From Conditions
DMA Channel Condition Determination 5.10 DMA Channel Condition Determination Several condition status flags are available to inform you of significant events or potential problems in DMA channel operation. These flags reside in the DMA channel secondary control register. These registers also provide the means to enable the DMA channels to inter- rupt the CPU through their corresponding interrupt enable (IE) fields.
Page 122: Dma Channel Condition Descriptions
DMA Channel Condition Determination 5.10.1 Definition of Channel Conditions Table 5–10 describes each of the condition flags in the DMA channel second- ary control register. Depending on the system application, these conditions can represent errors. The last frame condition can be used to change the reload register values for autoinitialization.
Page 123: Dma Controller Data Bus Block Diagram
DMA Controller Structure 5.11 DMA Controller Structure Figure 5–14 shows the internal data movement paths of the DMA controller, including data buses and internal holding registers. Figure 5–14. DMA Controller Data Bus Block Diagram Burst FIFO CH0 holding CH1 holding EMIF write EMIF read Data memory write...
Page 124 DMA Controller Structure 5.11.2 DMA FIFO A 9-level DMA FIFO holding path facilitates bursting to high-performance memo- ries, such as internal program and data memory, as well as external synchronous DRAM (SDRAM) or synchronous burst SRAM (SBSRAM). When combined with a channel’s holding registers this path effectively becomes an 11-level FIFO.
Page 125 DMA Controller Structure a resource and the DMA controller controls the rate of consecutive requests and the latency of received read transfer data. The other function of the DMA FIFO is capturing read data from any pending requests for a particular resource. For example, consider the situation in which the DMA controller is reading data from pipelined external memory such as SDRAM or SBSRAM into internal data memory.
Page 126 DMA Controller Structure / DMA Action Complete Pins / Emulation DMA Action Complete Pins 5.11.4 DMA Performance The DMA controller can perform element transfers with single-cycle throughput if it accesses separate resources for the read transfer and write transfer and both these resources have single-cycle throughput. An example is an unsynchronized block transfer from single-cycle external SBSRAM to internal data memory without any competition from any other channels or the CPU.
Page 127 Chapter 6 EDMA Controller This chapter describes the new enhanced DMA controller for the TMS320C6211/C6711. EDMA transfer parameters, types and performance are discussed. This chapter also describes the new quick DMA for fast data requests. Topic Page Overview ........... . . EDMA Terminology .
Page 128: Tms320C6211/C6711 Block Diagram
Overview 6.1 Overview The TMS320C6211/C6711 device performs data transfers between on-chip and/or off-chip locations using either the CPU or the enhanced direct memory access (EDMA) controller. Typically, block data transfers and transfer re- quests from peripherals are performed by the EDMA thus relieving the CPU to do performance-intensive operations.
Page 129: Edma Controller
Overview The EDMA controller comprises: Event and interrupt processing registers Event encoder Parameter RAM, and Address generation hardware A block diagram of the EDMA controller is shown in Figure 6–2. Figure 6–2. EDMA Controller Address to EMIF/peripherals Generation EDMA parameter RAM Channel 0 params Channel 1 params Channel 15 params...
Page 130 Overview EDMA events are captured in the event register. An event is a synchronization signal that triggers an EDMA channel to start a transfer. If events occur simultaneously, they are resolved by way of the event encoder. The transfer parameters corresponding to this event which is stored in the EDMA parameter RAM, are passed onto the address generation hardware, which address the EMIF and/or peripherals to perform the necessary read and write transactions.
Page 131 EDMA Terminology 6.2 EDMA Terminology The following definitions help in understanding some of the terms used in this chapter: Element transfer: The transfer of a single data element from source to destination. Each element can be transferred based on a sync event if required.
Page 132 Event Processing and EDMA Control Registers 6.3 Event Processing and EDMA Control Registers Each of the 16 channels in the EDMA have specific events associated with them. These events trigger the data transfer associated with that channel. The list of control registers that perform various processing of events is shown in Table 6–1.
Page 133: Event Register
Event Processing and EDMA Control Registers Once an event has been posted in the ER, the event can be cleared in two ways. If the event is enabled in the event enable register (EER), the corre- sponding event bit in the ER is cleared as soon as the EDMA submits a transfer request for that event.
Page 134 Event Encoder Event Processing and EDMA Control Register / Event Encoder Figure 6–5. Event Clear Register (ECR) Reserved R, +0 EC15 EC14 EC13 EC12 EC11 EC10 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 Figure 6–6.
Page 135 Parameter RAM (PaRAM) 6.5 Parameter RAM (PaRAM) Unlike the existing ‘C6201 DMA controller which is a register-based architec- ture, the enhanced DMA controller is a RAM-based architecture. The parame- ter RAM as the name indicates is used to store the parameters that define a particular EDMA transfer.
Page 136: Edma Parameter Ram Contents
Parameter RAM (PaRAM) Table 6–2. EDMA Parameter RAM Contents Address Event Parameters 01A0 0000h Event 0, options 01A0 0004h Event 0, SRC address 01A0 0008h Event 0, array/frame count Event 0, element count 01A0 000Ch Event 0, DST address 01A0 0010h Event array/frame index 0, Event 0, element index 01A0 0014h...
Page 137 Parameter RAM (PaRAM) Table 6–2. EDMA Parameter RAM Contents (Continued) Address Event Parameters 01A0 0120h to Parameters for event 12 (6 words) 01A0 0134h 01A0 0138h to Parameters for event 13 (6 words) 01A0 014Ch 01A0 0150h to Parameters for event 14 (6 words) 01A0 0164h 01A0 0168h to Parameters for event 15 (6 words)
Page 138: Parameter Storage For An Edma Event
Parameter RAM (PaRAM) 6.5.1 EDMA Transfer Parameter Entry Each parameter entry of an EDMA event is organized in six 32-bit words or 192 bits as shown in Figure 6–7. Access to the EDMA parameter RAM is provided only via the 32-bit peripheral bus. Figure 6–7.
Page 139 EDMA Transfer Parameters 6.6 EDMA Transfer Parameters Depending on the parameter options associated with a transfer, the source/destination address, element/array/frame count can be updated by the EDMA. The following sections describe the various parameters shown in Table 6–3. 6.6.1 Options Parameter The options parameter in the EDMA channel/event entry is a 32-bit field as shown in Figure 6–8.
Page 140 EDMA Transfer Parameters Table 6–3. EDMA Channel Options Field Description (Continued) Field Description Section TCINT Transfer complete interrupt 6.13 TCINT=0; Transfer complete indication disabled. CIPR bits are not set upon completion of a transfer. TCINT=1; The relevant CIPR bit is set on channel transfer completion.
Page 141 EDMA Transfer Parameters 6.6.3 Element Count Element count is a 16-bit unsigned value that specifies the number of elements in a frame (non-2D) or an array (for 2D transfers). Valid values for the element count can be anywhere between 1 and 65535. Therefore, the maximum num- ber of elements in a frame is 65535.
Page 142 EDMA Transfer Parameters 6.6.7 Link Address The EDMA controller provides a mechanism to link EDMA transfers. This is analogous to the auto-initialization feature in the DMA. The 16-bit link address specified in the EDMA parameter RAM specifies the lower 16-bit address in the parameter RAM from which the EDMA loads/reloads the parameters of the next event in the chain.
Page 143 Initiating an EDMA Transfer 6.7 Initiating an EDMA Transfer There are two ways to initiate data transfer using the EDMA. One is CPU-initi- ated EDMA and the other is an event-triggered EDMA. The latter is a more typi- cal usage of the EDMA. Each EDMA channel can be started independently. The CPU can also disable an EDMA channel by disabling the event associated with that channel.
Page 144: Edma Channel Association With Sync Events
Initiating an EDMA Transfer Events originate from a peripheral such as the McBSP (R/XEVT), or an exter- nal device in the form of an external interrupt (say, EXT_INT4). The source of these events is listed in Table 6–4. The event is specific to a channel, the prior- ity of each event can be specified independently in the transfer parameters stored in the EDMA parameter RAM.
Page 145 Initiating an EDMA Transfer There are two types of synchronization that can be used to synchronize trans- fers on each channel. They are: Read/write synchronization (R/WSYNC, FS=0): For non-2D transfers, each EDMA channel performs a source to destination element transfer only after receiving a read/write sync event.
Page 146 Types of EDMA Transfers 6.8 Types of EDMA Transfers The EDMA provides for two types of data transfers, namely non-2-dimensional (non-2D) and 2-dimensional (2D) transfers. This is selected by setting the 2DD and 2DS bits in the event’s options field. 2DD when set to 1 represents two-di- mensional transfer on the destination.
Page 147: Non-2D R/W Sync Edma Transfer Without Frame Sync
Types of EDMA Transfers Figure 6–9. Non-2D R/W Sync EDMA Transfer Without Frame Sync EC=1 ECRLD R/WSYNC +EIX +FIX Frame 0 EC=1 ECRLD +EIX R/WSYNC +FIX Frame 1 EC=1 +EIX FC=0 R/WSYNC Frame 2 6.8.1.2 Frame Synchronized Non-2D Transfer (FS=1) Figure 6–10 shows the concept of a non-2D EDMA transfer with frame syn- chronization.
Page 148: Non-2D Edma Transfer With Frame Sync
Types of EDMA Transfers Figure 6–10. Non-2D EDMA Transfer With Frame Sync EC=1 +EIX FS=1 Frame 0 EC=1 +EIX FS=1 Frame 1 EC=1 FC=0 +EIX FS=1 Frame 2 6.8.2 2-Dimensional Transfers 2-dimensional transfers are useful for imaging applications where contiguous set of elements (referred to as array) has to be transferred on receiving a sync event.
Page 149: Read/Write Synchronized 2-D Transfer (No Frame Sync)
Types of EDMA Transfers Figure 6–11.Read/Write Synchronized 2-D Transfer (No Frame Sync) EC=1 First dimension R/WSYNC (FS=0) Array 0 EC=1 R/WSYNC (FS=0) Array 1 EC=1 FC=0 R/WSYNC (FS=0) Array 2 6.8.2.2 Frame Synchronized 2D Transfer (FS=1) An example 2-dimensional block transfer with frame sync is shown in Figure 6–12.
Page 150 Types of EDMA Transfers The complete block gets transferred when the channel’s event occurs and FS=1. Note that the frame index (FIX) is added to the last element address in an array to derive the next array start address. This address update is trans- parent to the user and does not reflect in the parameter RAM.
Page 151 Linking EDMA Transfers 6.9 Linking EDMA Transfers The EDMA controller provides a mechanism known as ‘linking’, which allows multiple EDMA transfers to be linked. The completion of one transfer links the next transfer in a link causing its event parameters to be loaded from a location within the parameter RAM.
Page 152: Link Conditions
Linking EDMA Transfers The link address is evaluated only if LINK is equal to 1 and only after the event parameters have been exhausted. An event’s parameters are exhausted when the EDMA controller has completed the transfer associated with the re- quest.
Page 153 Element Size and Alignment 6.10 Element Size and Alignment The ESIZE field in the options of an event parameter entry allows the user to specify the element size that the EDMA should use for a transfer. The EDMA controller can transfer 32-bit words, 16-bit half-words, or 8-bit bytes in a trans- fer.
Page 154: Edma Element And Frame/Array Count Updates
Element and Frame/Array Count Updates 6.11 Element and Frame/Array Count Updates The EDMA parameter RAM has 16-bit unsigned values of element count (EC) and frame count (FC) each. Additionally, it also holds 16-bit signed values each for the element index (EIX) and frame index (FIX). The maximum number of elements in a frame or an array (for 2D transfers) is 65535.
Page 155 Src/Dst Address Updates 6.12 Src/Dst Address Updates Depending on the SUM/DUM fields in the options word of EDMA transfer pa- rameters, the source and/or destination addresses can be modified. The EDMA controller performs the necessary address computation. The various address update modes listed in Table 6–3 provide for a variety of data struc- tures that can be created.
Page 156: Edma Src Address Parameter Updates
Src/Dst Address Updates Table 6–7. EDMA SRC Address Parameter Updates Source Update Mode (SUM) Transfer- Type Frame (2DS:2DD) Sync FS = 0 None +ESIZE; –ESIZE; +EIX or +FIX if EC=1; Increment by element size Decrement by Add signed EIX to element size each element in a frame except the last.
Page 157: Edma Dst Address Parameter Updates
Src/Dst Address Updates Table 6–8. EDMA DST Address Parameter Updates Destination Update Mode (DUM) Frame Transfer Type Sync (2DS:2DD) FS = 0 None +ESIZE; –ESIZE; +EIX or +FIX if EC = 1 Increment by element Decrement by element Add signed EIX to each size.
Page 158 EDMA Interrupt Generation 6.13 EDMA Interrupt Generation The EDMA controller is responsible for generating channel-complete interrupts to the CPU. Unlike the ’C6201 DMA controller which has individual interrupts for each DMA channel, the EDMA generates a single interrupt (EDMA_INT) to the CPU on behalf of all 16 channels. The various control reg- isters and bit fields facilitate EDMA interrupt generation.
Page 159: Transfer Complete Code (Tcc) To Dma Interrupt Mapping
EDMA Interrupt Generation The TCC field can have values between 0000b to 1111b. These are directly mapped to the CIPR bits as shown in Table 6–9. For example, if TCC = 1100b, CIPR[12] is set to 1 after the transfer is complete, and this generates a CPU interrupt only if CIER[12] = 1.
Page 160 EDMA Interrupt Generation 6.13.1 EDMA Interrupt Servicing by the CPU Since the EDMA controller is aware when the EDMA channel transfer is com- plete, it sets the appropriate bit in the CIPR as per the TCC specified by the user. The CPU ISR should read the CIPR and determine what, if any events/ channels have completed and perform the operations necessary.
Page 161: Channel Chain Enable Register (Ccer)
EDMA Interrupt Generation Figure 6–16. Channel Chain Enable Register (CCER) rsvd CCE11 CCE10 CCE9 CCE8 rsvd R, +0 RW, +0 RW, +0 RW, +0 RW, +0 R, +0 For example, if TCC = 1000b and CCER[8] = 1 is specified for EDMA channel 4, an external interrupt on EXT_INT4 initiates the EDMA transfer.
Page 162 Resource Arbitration and Priority Processing 6.14 Resource Arbitration and Priority Processing The 16 EDMA channels can have programmable priority in the two lower levels. The PRI bit in options specifies the two priority levels: level1 (high prior- ity, PRI = 001b) and level 2 (low priority, PRI = 010b). The highest priority avail- able in the system is level 0 or the urgent priority, which is dedicated to L2 re- quests.
Page 163: Priority Queue Status Register(Pqsr)
Resource Arbitration and Priority Processing / EDMA Performance EDMA Performance The priority queue status register (PQSR) shown in Figure 6–17 indicates if the transfer request queue is empty on the three priority levels ( 0 – urgent, 1 – high, and 2 – low). EDMA transfers can be submitted only with priority level one or two.
Page 164 Quick DMA (QDMA) 6.16 Quick DMA (QDMA) QDMA, or quick DMA, provides one of the most efficient ways to move data around in the ’C6211 architecture. Quick DMA supports nearly all of the same transfer modes of the EDMA. However, as the name implies, QDMA submits transfer requests more quickly than the EDMA.
Page 165 Quick DMA (QDMA) Figure 6–19. QDMA Pseudo Registers QDMA_S_OPT QDMA options 0200 0020h QDMA_S_SRC SRC address 0200 0024h QDMA_S_CNT Arrary/frame count Element count 0200 0028h QDMA_S_DST DST address 0200 002Ch QDMA_S_IDX Arrary/frame index Element index 0200 0030h The QDMA options register shown in Figure 6–20 is similar to the options parameter in the EDMA parameter RAM, which is shown in Figure 6–8 and described in Table 6–3.
Page 166 Quick DMA (QDMA) TCC field can have values between 0000b to 1111b, just as the TCC field in the EDMA options parameter. Please refer to section 6.13 for detail. Similar to the EDMA, the QDMA completion event is captured in the EDMA channel interrupt pending register (CIPR).
Page 167 Quick DMA (QDMA) sible to submit the first QDMA request in as little as five cycles (one cycle write for each of the five QDMA registers), as opposed to 36 cycles for the first EDMA transfer request (6-cycle store for each of the six EDMA transfer param- eters).
Page 168 Chapter 7 Host-Port Interface This chapter describes the host-port interface that external processors use to access the memory space. The host port control registers and signals are de- scribed. Topic Page Overview ........... . . HPI Signal Descriptions .
Page 169 HPI address register (HPIA), the HPI data register (HPID), and the HPIC by using the external data and interface control signals. Figure 7–1 shows the host-port components in the block diagram of the on- chip peripherals. Figure 7–1. TMS320C6201/C6701 Block Diagram Timers Data memory Interrupt selector...
Page 170: Tms320C6211/C6711 Block Diagram
Overview As with the ‘C6201/’C6701 HPI, the ’C6211/C6711 HPI allows an external host processor to perform read and write accesses from/to the ‘C6211/C6711 ad- dress space. Unlike the ‘C6201 HPI interface which uses the DMA auxiliary channel to perform accesses, the ’C6211/C6711 the HPI ties directly into inter- nal address generation hardware.
Page 171: Hpi Block Diagram
Overview Figure 7–3 is a simplified diagram of the ’C6201/’C6701 HPI. The HPI provides 32-bit data to the CPU with an economical 16-bit external interface by automatically combining successive 16-bit transfers. When the host device transfers data through HPID, the DMA auxiliary channel accesses the CPU’s address space.
Page 172: Hpi Block Diagram Of Tms320C6211/C6711
Overview The pin interface is similar to the ‘C6201 HPI interface as shown in Figure 7–4 except for the byte enables (/HBE[1:0] in ’C6201/’C6701) which are not sup- ported. All accesses through the 16-bit data bus HD[15:0] have to be in pairs. Figure 7–4.
Page 173 Overview The HPI ready pin (HRDY) allows insertion of host wait states. Wait states may be necessary, depending on latency to the point in the memory map accessed via the HPI, as well as on the rate of host access. The rate of host access can force not-ready conditions if the host attempts to access the host port before any previous HPID write access or prefetched HPID read access finishes.
Page 174: Hpi External Interface Signals
HPI Signal Descriptions 7.2 HPI Signal Descriptions The external HPI interface signals implement a flexible interface to a variety of host devices. Table 7–1 lists the HPI pins and their functions. The remainder of this section discusses the pins in detail. Table 7–1.
Page 175: Hpi Input Control Signals Function Selection Descriptions
HPI Signal Descriptions Table 7–2. HPI Input Control Signals Function Selection Descriptions HCNTL1 HCNTL0 Description Host reads from or writes to the HPI control register (HPIC). Host reads from or writes to the HPI address register (HPIA). Host reads or writes to the HPI data register (HPID). The HPI address register (HPIA) is postincremented by a word ad- dress (four byte addresses).
Page 176 HPI Signal Descriptions 7.2.4 Byte Enables: HBE[1:0] On HPID writes, the value of HBE[1:0] indicates which bytes of the 32-bit word are written. The value of HBE[1:0] is not important on HPIA or HPIC accesses or on HPID reads. On HPID writes, HBE0 enables the least significant byte in the halfword and HBE1 enables the most significant byte in the halfword.
Page 177: Byte Enables For Hpi Data Write Access
HPI Signal Descriptions Table 7–4. Byte Enables for HPI Data Write Access HBE[1:0] First Write Second Write Effective Logical Address HWOB = 0 HHWIL = 0 HHWIL = 1 LSBs (Binary) Data Write Second Write First Write HWOB = 1 Little Endian Big Endian Type HHWIL = 1...
Page 178: Select Input Logic
HPI Signal Descriptions Figure 7–5 shows the equivalent circuit of the HCS, HDS1, and HDS2 inputs. Figure 7–5. Select Input Logic HDS1 HDS2 HSTROBE (internal signal) Used together, HCS, HDS1, and HDS2 generate an active (low) internal HSTROBE signal. HSTROBE is active (low) only when both HCS is active and either (but not both) HDS1 or HDS2 is active.
Page 179 HPI Signal Descriptions 7.2.8 Address Strobe Input: HAS HAS allows HCNTL[1:0], HR/W, and HHWIL to be removed earlier in an ac- cess cycle, which allows more time to switch bus states from address to data information. This feature facilitates interface to multiplexed address and data buses.
Page 180 HPI Signal Descriptions When low, HRDY indicates that the HPI is ready for a transfer to be performed. HCS enables HRDY, and HRDY is always low when HCS is high. Case 1 in Figure 7–6 and Figure 7–7, where HRDY goes high when HCS falls, indicates that the HPI is busy completing a previous HPID write or read with autoincre- ment.
Page 181: Hpi Read Timing (Has Not Used, Tied High)
HPI Signal Descriptions Figure 7–6. HPI Read Timing (HAS Not Used, Tied High) HCNTL[1:0] HR/W HHWIL HSTROBE HD[15:0] (output) 1st halfword 2nd halfword HRDY (case 1) HRDY (case 2) Figure 7–7. HPI Read Timing (HAS Used) HCNTL[1:0] HR/W HHWIL HSTROBE HD[15:0] (output) 1st halfword 2nd halfword...
Page 182: Hpi Write Timing (Has Not Used, Tied High)
HPI Signal Descriptions Figure 7–8. HPI Write Timing (HAS Not Used, Tied High) HCNTL[1:0] HBE[1:0] HR/W HHWIL HSTROBE HD[15:0] 1st halfword 2nd halfword HRDY Figure 7–9. HPI Write Timing (HAS Used) HBE[1:0] HCNTL[1:0] HR/W HHWIL HSTROBE HD[15:0] 1st halfword 2nd halfword HRDY Host-Port Interface 7-15...
Page 183: Hpi Registers
HPI Registers 7.3 HPI Registers Table 7–5 summarizes the three registers that the HPI uses for communication between the host device and the CPU. HPID contains the data that was read from the memory accessed by the HPI if the current access is a read or the data that is written to the memory if the current access is a write.
Page 184: Hpic Register
HPI Registers Figure 7–10. HPIC Register rsvd HRDY HINT DSPINT HWOB HR,CR,+0 HRW,CR,+0 HR,CR,+0 HRW,CR,+0 HRW,CR,+0 HRW,CR,+0 rsvd FETCH HRDY HINT DSPINT HWOB HR,CR,+0 HRW,CR,+0 HR,CR,+1 HRW,CRW,+0 HRW,CRW,+0 HRW,CR,+0 Table 7–6. HPI Control Register (HPIC) Bit Descriptions Description Section HWOB Halfword ordering bit If HWOB = 1, the first halfword is least significant.
Page 185 HPI Registers 1) The host polls the HPIC register for HRDY = 1. 2) The host writes the desired HPIA value. This step is skipped if HPIA is already set to the desired value. 3) The host writes a 1 to the FETCH bit. 4) The host polls again for HRDY = 1.
Page 186: Initialization Of Hwob = 1 And Hpia
Host Access Sequences 7.4 Host Access Sequences The host begins HPI accesses by performing the following tasks in the order giving: 1) Initializing the HPIC register 2) Initializing the HPIA register 3) Writing data to or reading data from HPID register Reading from or writing to HPID initiates an internal cycle that transfers the de- sired data between the HPID register and the DMA auxiliary channel.
Page 187: Initialization Of Hwob = 0 And Hpia
Host Access Sequences Table 7–8. Initialization of HWOB = 0 and HPIA Value During Access Value After Access Event HBE[1:0] HR/W HCNTL[1:0] HHWIL HPIC HPIA HPID Host writes HPIC 0000 00080008 ???????? ???????? 1st halfword Host writes HPIC 0000 00080008 ???????? ???????? 2nd halfword Host writes HPIA 8000...
Page 188: Data Read Access To Hpi Without Autoincrement: Hwob
Host Access Sequences Table 7–9. Data Read Access to HPI Without Autoincrement: HWOB = 1 Value During Access Value After Access HBE[1:0] HR/W HCNTL[1:0] HHWIL HPIC HPIA HPID Event Host reads ???? 00010001 80001234 ???????? HPID 1st half- word Data not ready Host reads BCDE 00090009 80001234 789ABCDE...
Page 189: Read Access To Hpi With Autoincrement: Hwob
Host Access Sequences 7.4.3 HPID Read Access With Autoincrement The autoincrement feature results in efficient sequential host accesses. For both HPID read and write accesses, this removes the need for the host to load incremented addresses into HPIA. For read accesses, the data pointed to by the next address is fetched immediately after the completion of the current read.
Page 190: Read Access To Hpi With Autoincrement: Hwob
Host Access Sequences Table 7–12. Read Access to HPI With Autoincrement: HWOB = 0 Value During Access Value After Access Event HBE[1:0] HR/W HCNTL[1:0] HRDY HHWIL HPIC HPIA HPID Host reads ???? 00000000 80001234 ???????? 1st halfword Data not ready Host reads 789A 00080008...
Page 191: Data Write Access To Hpi Without Autoincrement: Hwob
Host Access Sequences Table 7–13. Data Write Access to HPI Without Autoincrement: HWOB = 1 Value During Access Value After Access Location Location HBE[1:0] HR/W HCNTL[1:0] HRDY HHWIL HPIC HPIA HPID 80001234 Event Host writes HPID 5566 00010001 80001234 ???????? 00000000 1st halfword Waiting for previous...
Page 192: Write Access To Hpi With Autoincrement: Hwob
Host Access Sequences 7.4.5 HPID Write Access With Autoincrement Table 7–15 and Table 7–16 summarize a host data write with autoincrement for HWOB = 1 and HWOB = 0, respectively. These examples are identical to the ones in section 7.4.4, except for the HCNTL[1:0] value and a subsequent write of 33h to the most significant byte of the word at address 8000 1238h.
Page 193: Write Access To Hpi With Autoincrement: Hwob
Host Access Sequences Table 7–16. Write Access to HPI With Autoincrement: HWOB = 0 Value During Access Value After Access HCNTL Location Location [1:0] [1:0] HR/W HRDY HHWIL HPIC HPIA HPID 80001234 80001238 Event Host writes wxyz 00000000 80001234 ???????? 00000000 00000000 HPID...
Page 194 Host Access Sequences / Memory Access Through the HPI During Reset Memory Access Through the HPI During Reset Writes to and reads from HPIA: In Table 7–7, the portion of HPIA accesses selected by HHWIL and HWOB is updated automatically after each half- word access.
Page 195 Chapter 8 Expansion Bus This section describes the expansion bus used by CPU to access off-chip peripherals, FIFOs and PCI interface chips. Topic Page Overview ........... . . Expansion Bus Signals .
Page 196 Overview 8.1 Overview The expansion bus is a 32-bit wide bus that supports interfaces to a variety of asynchronous peripherals, asynchronous or synchronous FIFOs, PCI bridge chips, and other external masters. The expansion bus offers a flexible bus arbitration scheme, implemented with two signals, XHOLD and XHOLDA.
Page 197 Overview The I/O port has two modes of operation, which can coexist in a single system: asynchronous I/O mode and synchronous FIFO mode. These modes are selectable for each of expansion bus’s four XCE spaces. The first mode (asynchronous I/O mode) provides output strobes, which are highly programmable like the asynchronous signals of the external memory interface (EMIF).
Page 198: The Expansion Bus Interface In The Tms320C6202 Block Diagram
Overview Figure 8–2. The Expansion Bus Interface in the TMS320C6202 Block Diagram C6202 digital signal processor Internal program memory Program 1 block program/cache 1 access/ block mapped program Program bus cache (128k bytes each) controller External (256k bytes total) memory interface (EMIF) C6200B CPU...
Page 199: Expansion Bus Signals
Expansion Bus Signals 8.2 Expansion Bus Signals Table 8–1 lists the expansion bus signals and their functionality in each mode. Table 8–1. Expansion Bus Signals I/O Port Mode Mutually Exclusive (Non-Exclusive) Host Port Modes Async Sync FIFO Sync Expansion (I/O/Z) Signal (I/O/Z) Signal...
Page 200: Expansion Bus Memory Mapped Registers
Expansion Bus Registers 8.3 Expansion Bus Registers Control of the expansion bus and the peripheral interfaces is maintained through memory-mapped registers within the expansion bus. The memory- mapped registers are shown in Table 8–2. Table 8–2. Expansion Bus Memory Mapped Registers Byte Address Name 0188 0000 h...
Page 201: Expansion Bus Host Port Registers
Expansion Bus Registers 8.3.1 Expansion Bus Host Port Registers The external master on the expansion bus uses the XCNTL signal to select which internal register is being accessed. The state of this pin selects whether access is made to the expansion bus internal slave address (XBISA) register or, expansion bus data (XBD) register.
Page 202: Expansion Bus Global Control Register
Expansion Bus Registers 8.3.2 Expansion Bus Global Control Register The expansion bus global control register (shown in Figure 8–3, and de- scribed in Table 8–4) configures parameters of the expansion bus common to all interfaces. Figure 8–3. Expansion Bus Global Control Register Reserved FMOD XFCEN...
Page 203: Xce Space Control Registers
Reserved The remaining fields are defined in detail in chapter 6, external memory inter- face in the TMS320C6201/6701 Peripheral Reference Guide (SPRU190B). These fields are specific to the asynchronous interface and are functionally equivalent to the fields in the EMIF CE space control registers.
Page 204: 8.4 Expansion Bus I/O Port Operation
Expansion Bus I/O Port Operation 8.4 Expansion Bus I/O Port Operation For external IO port accesses on the expansion bus, the XBE signals act as address signals XA[5:2]. You can use the address signals to address as many as 16 different R/W peripherals or 32 FIFOs in each XCE space. For the FIFO interface, 32 devices are possible since a separate Read and Write FIFO can be located at each address.
Page 205: Example Of The Expansion Bus Interface To Four 8-Bit Fifos
Expansion Bus I/O Port Operation Figure 8–5 illustrates how to interface four 8-bit FIFOs to the I/O port (memory map for this case is described in Table 8–7). Figure 8–6 is an example of inter- face between two 16-bit FIFOs and the I/O port. Figure 8–5.
Page 206: Asynchronous Mode
Expansion Bus I/O Port Operation Figure 8–6. Example of the Expansion Bus Interface to Two 16-Bit FIFOs FIFO #1 XFCLK D[15:0] XD[15:0] FIFO #2 XD[31:0] XD[31:0] XD[31:16] D[15:0] XA[2] Table 8–7. Addressing Scheme – Case When the Expansion Bus is Interfaced to Two 16-Bit FIFOs Logical Address A[31:6]...
Page 207: Synch Fifo Modes
Expansion Bus I/O Port Operation Notes: 1) XRDY is active (low) during host-port accesses. 2) XBE[3:0]/XA[5:2] operate as XBE[3:0] during host-port accesses. 8.4.2 Synch FIFO Modes The synchronous FIFO mode of the expansion bus offers a glueless and/or low glue interface to standard synchronous FIFOs. The expansion bus can interface up to four write FIFOs without using glue logic (one per XCE space) or three write FIFOs and a single read FIFO (in XCE3 only).
Page 208: Synch Fifo Pin Description
Expansion Bus I/O Port Operation Table 8–8. Synch FIFO Pin Description Signal Function Signal Signal R/W Mode Read Mode (I/O/Z) Signal Purpose Name XFCLK FIFO clock output Programmable to either 1/2, 1/4, 1/6, or 1/8 of the CPU clock frequency. If CPU clock = 250 MHz, then XFCLK = 125, 62.5, 41.7 or 31.25 MHz.
Page 209: Glueless Write Fifo Interface
Expansion Bus I/O Port Operation 8.4.2.1 Write Interface During write accesses to a memory space configured for read/write FIFO mode, the XCE signal and XWE signal are both active for a single rising edge of XFCLK. So, depending on the specific system environment, the write interface can be accomplished either with glue or without glue.
Page 210: Read And Write Fifo Interface With Glue
Expansion Bus I/O Port Operation Figure 8–8. Read and Write FIFO Interface With Glue XFCLK RCLK WCLK XCEx Synchronous Expansion FIFO EXT_INTx Q[31:0] D[31:0] EXT_INTy XD[31:0] WCLK RCLK Synchronous FIFO Q[31:0] Q[31:0] Figure 8–9. FIFO Write Cycles XFCLK XCEx XBE[3:0] / XA[5:2] WEN = XCEx + XWE XD[31:0] 8-16...
Page 211: Glueless Read Fifo Interface
Expansion Bus I/O Port Operation 8.4.2.2 Read FIFO Interface The read FIFO interface can be accomplished gluelessly in XCE3 space or with a small amount of glue in any XCE space. If a glueless read FIFO interface is used (specified by boot configuration selection), the XOE signal is only en- abled in XCE3 space, and is dedicated to use for the FIFO interface.
Page 212: Fifo Read Mode - With Glue
Expansion Bus I/O Port Operation Figure 8–12. FIFO Read Mode – With Glue XFCLK XCEx XBE[3:0], XA[5:2] REN = XCEx + XRE OE = XCEx + XOE XD[31:0] 8.4.2.3 Programming Offset Register The programmable offset registers of the FIFO are used to hold the offset val- ues for the flags that indicate the condition of the FIFO contents.
Page 213 Expansion Bus I/O Port Operation 8.4.2.4 Flag Monitoring To efficiently control bursts to and from the dedicated FIFO interfaces, the in- terrupt signals EXT_INT4, EXT_INT5, EXT_INT6, and EXT_INT7 are used as flags to control DMA transfers. The flag polarity used to start transfer can be programmed in the DMA secondary control register.
Page 214: Dma Transfer Examples
Expansion Bus I/O Port Operation 8.4.3 DMA Transfer Examples 8.4.3.1 Example 1 (single frame transfer) Peripherals located on the I/O port of the expansion bus are accessible only via DMA transactions. This section gives a very simple example used to trans- fer a single frame of 256 words from a FIFO located in XCE0 into internal data memory at 8000 0000h.
Page 215: Content Of Relevant Registers (Multiple Frame Transfer)
Expansion Bus I/O Port Operation 8.4.3.2 Example 2 (transfer with frame synchronization) In this example ten frames of 256 words from a FIFO located in XCE0 are transferred into internal data memory at 8000 0000h. This example simply sets up the source and destination registers, and starts the DMA with incre- menting destination address and a non-changing source address.
Page 216: 8.5 Expansion Bus Host Port Operation
Expansion Bus Host Port Operation 8.5 Expansion Bus Host Port Operation The expansion bus host port has two modes, which enable interfaces to exter- nal processors, PCI bridge chips, or other external peripherals. These are the synchronous host port mode and the asynchronous host port mode. The syn- chronous host port mode can interface with minimum glue to PCI bridge chips and many common microprocessors.
Page 217: Expansion Bus Host Port Registers Description
Expansion Bus Host Port Operation 8.5.1 Expansion Bus Host Port Registers Description 8.5.1.1 Expansion Bus Data Register The expansion bus data (XBD) register, shown in Figure 8–14, contains the data that was read from the memory accessed by the expansion bus host port if the current access is a read, or the data that is written to the memory if the current access is a write.
Page 218: Expansion Bus External Address Register
Expansion Bus Host Port Operation This register is used when the host port operates either in synchronous or asynchronous mode. The ’C6202 does not have access to the XBISA register content. Burst transfers in the synchronous host-port mode are always expected to occur with autoincrement (AINC bit should be set to zero).
Page 219: Xbhc Register Description
Expansion Bus Host Port Operation The START bit field in the XBHC register is not cleared to zero after a transfer is completed. Writing ’00’ to the the START field, when a transfer in progress is stalled by XRDY high, aborts the transfer. When a transfer is aborted the XBIMA and XBEA registers and the XFRCT transfer counter reflect the state of the aborted transfer.
Page 220: Synchronous Host Port Mode
Expansion Bus Host Port Operation 8.5.2 Synchronous Host Port Mode In this mode host port has address and data signals multiplexed and is i960Jx compatible. This allows a minimum glue interface to the PCI bus, since major PCI interface chip manufacturers adopted the i960 bus for local bus on their chips.
Page 221 Expansion Bus Host Port Operation Table 8–16. Expansion Bus Pin Description (Synchronous Host Port Mode) (Continued) Signal Signal Signal Signal Signal Function Symbol Type Count Name XD[31:0] I/O/Z Address/ Data data bus XBLAST I/O/Z Burst last Signal driven by the current expansion bus master to indicate the last transfer in a bus access.
Page 222 Expansion Bus Host Port Operation 8.5.2.1 TMS320C6202 Master on the Expansion Bus When the ‘C6202 is the master of the expansion bus, it can initiate a burst read or write to a peripheral on the bus. When the DSP controls the bus, data flow is controlled in a manner similar to a DMA transfer;...
Page 223: Read Transfer Initiated By The Tms320C6202 And Throttled By
Expansion Bus Host Port Operation Burst Read Transfer The timing presented in Table 8–16 can be referenced for a visual description of the steps required to complete a burst read initiated by the ’C6202 and throttled by the XWAIT and XRDY signals. Figure 8–19.
Page 224 Expansion Bus Host Port Operation 5) Data phase: The external device is not ready to deliver data, as indicated by XRDY high. 6) Same as 5. 7) Same as 5. 8) Same as 5. 9) The external device presents requested data (D1), and asserts XRDY. 10) The external device is not ready to deliver next data.
Page 225: Write Transfer Initiated By The Tms320C6202 And Throttled By
Expansion Bus Host Port Operation Burst Write Transfer The timing presented in Figure 8–20 can be referenced for a visual description of the steps required to complete a burst write initiated by the C6202 and throttled by the XWAIT and XRDY signals. Figure 8–20.
Page 226 Expansion Bus Host Port Operation 5) Data phase: During this phase, data (D1) is presented by the DSP and the external device is ready to accept the data, which is indicated by XRDY being active. 6) The DSP presents next data (D2). The external device indicates not ready condition, which is indicated by XRDY being inactive.
Page 227: External Device Requests The Bus From The Tms320C6202 Using Xboff
Expansion Bus Host Port Operation Preventing Deadlocks with Backoff To prevent deadlocks while the ’C6202 is performing a master transfer, the ex- pansion bus has the XBOFF signal. When asserted, XBOFF suspends the current access and causes the ‘C6202 to release ownership of the expansion bus.
Page 228 Expansion Bus Host Port Operation The timing diagram shown in Figure 8–21 can be referenced for a visual description of the steps involved in release of the expansion bus ownership as initiated by the XBOFF signal. The diagram illustrates the backoff condition for both internal bus arbiter enabled and internal bus arbiter disabled .
Page 229 Expansion Bus Host Port Operation 8.5.2.2 TMS320C6202 Slave on the Expansion Bus The external host can access the different expansion bus host port registers by driving the XCNTL signal as follows: XCNTL = 0 Reads or writes the expansion bus data (XBD) register. XCNTL = 1 Reads or writes the expansion bus internal slave address (XBISA) register.
Page 230 Expansion Bus Host Port Operation Cycle Description Each access initiated by the external host can be broken up into distinct cate- gories: Address phase (Ta): During the address phase, the ’C6x is selected with the XCS input and the address phase is started with a low pulse on the XAS signal.
Page 231: The Expansion Bus Master Writes A Burst Of Data To The Tms320C6202
Expansion Bus Host Port Operation Burst Write Transfer The timing diagram shown in Figure 8–22 can be referenced for a visual description of the steps required to complete a burst write initiated by an external host and throttled by the XRDY signal. Figure 8–22.
Page 232 Expansion Bus Host Port Operation The step by step description of the events marked above the waveforms in Figure 8–22 follows: 1) The XCS, XAS and XCNTL signals are low, low, and high respectively, in- dicating XBISA register as the destination for the following transaction. The XW/R is high specifying that a write access is taking place.
Page 233: The Bus Master Reads A Burst Of Data From The Tms320C6202
Expansion Bus Host Port Operation Burst Read Transfer The timing diagram shown in Figure 8–23 can be referenced for a visual description of the steps required to complete a burst read initiated by an external host and throttled by the XRDY signal. Figure 8–23.
Page 234 Expansion Bus Host Port Operation The step by step description of the events marked above the waveforms in Figure 8–23 follows: 1) The XCS, XAS and XCNTL signals are low, low and high respectively, indicating XBISA register as the destination for the following transaction. The XW/R is high specifying that a write access is taking place.
Page 235: Asynchronous Host Port Mode
Expansion Bus Host Port Operation 8.5.3 Asynchronous Host Port Mode This mode is slave only, it uses a 32-bit data path, and it is similar to the HPI on the ‘C6201. The asynchronous host port mode is used to interface to asyn- chronous microprocessor buses.
Page 236 Expansion Bus Host Port Operation If the expansion bus host port operates in the asynchronous mode, every transaction initiated by the host on the expansion bus is a two step process. The host first has to set the XBISA register, and then transfer the data to/from the address pointed to by the XBISA register.
Page 237: Timing Diagrams For Asynchronous Host Port Mode Of The Expansion Bus
Expansion Bus Host Port Operation Figure 8–24. Timing Diagrams for Asynchronous Host Port Mode of the Expansion Bus Asynchronous Host Port Write Timing XCNTL (input) XBE[3:0] (input) XR/W (input) XCS (input) word XD[31:0] XRDY (output) Asynchronous Host Port Read Timing XCNTL (input) XBE[3:0] (input) XR/W (input)
Page 238: 8.6 Expansion Bus Arbitration
Expansion Bus Arbitration 8.6 Expansion Bus Arbitration Two signals, XHOLD and XHOLDA, are provided for bus arbitration. The internal bus arbiter is disabled or enabled depending on the value on the expansion data bus during reset. The XARB bit in the expansion bus global control register indicates if the inter- nal bus arbiter is enabled or disabled.
Page 239: Internal Bus Arbiter Disabled
Expansion Bus Arbitration Figure 8–25. Timing Diagrams for Bus Arbitration–XHOLD/XHOLDA (Internal Bus Arbiter Enabled). External Device Mastering the Bus XHOLD(input) XHOLDA(output) OUTPUTS 8.6.2 Internal Bus Arbiter Disabled In this mode, the ‘C6202 acts as slave on the expansion bus by default. This mode is preferred if the ‘C6202 is interfacing to an external host, or if multiple ‘C6202 are connected to a PCI interface chip.
Page 240: Xhold Timing When The External Host Starts A Transfer To Dsp Instead Of
Expansion Bus Arbitration Figure 8–27. XHOLD Timing When the External Host Starts a Transfer to DSP Instead of Granting the DSP Access to the Expansion Bus(Internal Bus Arbiter Disabled) XHOLD (output) XHOLDA (input) XAS (input) XCS (input) XBLAST (input) Table 8–19 shows possible scenarios that can happen when the internal bus arbiter is disabled (XARB =0).
Page 241 Expansion Bus Arbitration Table 8–19. Possible Expansion Bus Arbitration Scenarios (Internal Bus Arbiter Disabled) XARB = ’0’ Current External Host XBOFF Activity Current DSP state asserted Actions Actions DMA request to ex- The DSP asserts the XHOLD, and once it gets the ex- pansion Bus IO port pansion bus the transfer starts.
Page 242: Expansion Bus Requestor Priority
Expansion Bus Arbitration 8.6.3 Expansion Bus Requestor Priority For the expansion bus of the ‘C6202, the auxiliary DMA channel is always given the highest priority, followed by the standard DMA priority (DMA0 high- est). Priority Description Highest Auxiliary channel DMA0 DMA1 DMA2 Lowest...
Page 243: 8.7 Boot Configuration Control Via Expansion Bus
Boot Configuration Control via Expansion Bus 8.7 Boot Configuration Control via Expansion Bus The polarity of read/write XW/R and XBLAST control signals on the expansion bus is determined during boot using pull up/pull down resistors on the XD[31:0] pins of the expansion bus. Pull up/pull down resistors on the expansion bus are used for boot mode selection and to enable/disable internal bus arbiter, to define expansion bus host port mode to define memory type used in each expansion bus memory space and to define FIFO mode.
Page 244: Resistors On
Boot Configuration Control via Expansion Bus Table 8–20. Description of Expansion Bus Boot Configuration via Pull Up/Pull Down Resistors on XD[31:0] Field Description MTYPE0/1/2/3 Memory type MTYPE=010b: 32-bit wide asynchronous interface MTYPE=101b: 32-bit wide FIFO interface MTYPE=other: reserved BLPOL Determines polarity of the XBLAST signal when the DSP is a slave on the expansion bus.
Page 245: External Memory Interface
Chapter 9 External Memory Interface This chapter describes the external memory interface used by the CPU to access off-chip memory. This chapter also describes the EMIF control registers and their fields, and it explains how to reset the EMIF. Various memory interfaces are described, along with diagrams showing the connections between the EMIF and each supported memory type.
Page 246: 9.1 Overview
TMS320C6201/C6202/C6701 is shown in Figure 9–1, and the signals shown there are summarized in Table 9–1. The ’C6211/C6711 services requests of the external bus from two requestors: An enhanced direct-memory access (EMDA) controller An external shared-memory device controller...
Page 247 Overview Figure 9–1. External Memory Interface in the TMS320C6201/C6202/C6701BlockDiagram TMS320C6000 Timers Data memory Interrupt selector Peripheral McBSPs controller HPI control DMA control Data memory EMIF control controller Host port controller CPU core Program fetch Instruction dispatch Instruction decode Data path...
Page 248: Tms320C6201/C6701 External Memory Interface
Overview Figure 9–3. TMS320C6201/C6701 External Memory Interface CLKOUT1 CLKOUT2 ED[31:0] Shared by EA[21:2] all external CE[3:0] interfaces BE[3:0] controller ARDY Asynchronous interface External Data memory memory interface controller SSADS (EMIF) SSOE SBSRAM SSWE interface SSCLK Program memory SDRAS controller SDCAS...
Page 249: Tms320C6202 External Memory Interface
Overview The EMIF signals of the ’C6202 are shown in Figure 9–4. The ’C6202 has combined the SDRAM and SBSRAM signals, such that only one of these two memory types can be used in a system. These memories run off CLKOUT2, which is equal to 1/2x the CPU clock rate.
Page 250: Tms320C6211/C6711 External Memory Interface
Overview The EMIF signals of the ’C6211/C6711 are shown in Figure 9–5. The ’C6211/C6711 has the following features: The ’C6211/C6711 EMIF requires that an external clock source (ECLKIN) be provided by the system. The ECLKOUT signal is produced internally (based on ECLKIN). All of the memories interfacing with the ’C6211/C6711 should operate off of ECLKOUT.
Page 251: Emif Signal Descriptions
Overview Table 9–1. EMIF Signal Descriptions 1 Pin (I/O/Z) Description CLKOUT1 Clock output. Runs at the CPU clock rate. CLKOUT2 Clock output. Runs at 1/2 the CPU clock rate. Used for synchronous memory interface on ’C6202 BUSREQ Active high bus request signal ECLKOUT EMIF clock output.
Page 252: 9.2 Resetting The Emif
Resetting the EMIF 9.2 Resetting the EMIF A hardware reset using the RESET pin on the device forces all register values to their reset state. During reset, all outputs are driven to their inactive levels, with the exception of the clock outputs (SDCLK, SSCLK, CLKOUT1, and CLKOUT2).
Page 253: 9.3 Emif Registers
EMIF Registers 9.3 EMIF Registers Control of the EMIF and the memory interfaces it supports is maintained through memory-mapped registers within the EMIF. The memory-mapped registers are listed in Table 9–2. Table 9–2. EMIF Memory-Mapped Registers Byte Address Name 0180 0000h EMIF global control 0180 0004h EMIF CE1 space control...
Page 254: Emif Global Control Register Field Descriptions
EMIF Registers Table 9–3. EMIF Global Control Register Field Descriptions Field Description BUSREQ † BUSREQ = 0; BUSREQ ouput is low. BUSREQ = 1; BUSREQ output is high. ARDY ARDY = 0: ARDY input is low. ARDY = 1: ARDY input is high. HOLD HOLD = 0: HOLD input is low.
Page 255 EMIF Registers Table 9–3. EMIF Global Control Register Field Descriptions (Continued) Field Description SSCRT ‡ SBSRAM clock rate select SSCRT = 0: SSCLK runs at 1/2x CPU clock rate SSCRT = 1: SSCLK runs at 1x CPU clock rate There is no SSCLK on the ’C6202. CLKOUT2 is fixed at half the CPU clock.
Page 256: Emif Ce Space Control Registers
CE space memory type to asynchronous memory does not affect the memory type of other CE spaces, and setting a memory space to a synchronous type does not change the type of asynchronous memory spaces. Figure 9–7. TMS320C6201/C6202/C6701 EMIF CE Space Control Register Diagram 20 19 Write setup...
Page 257: Emif Ce Space Control Registers Field Descriptions
Turn around time controls the number of ECLKOUT cycles between a read, and a write, or between reads, to different CE spaces (asynchronous memory types only). ‡ † Applies to TMS320C6201/C6202/C6701 ‡ Applies to TMS320C6211/C6711 § Clock cycles are in terms of CLKOUT1 for ’C6201/C6202/C6701, and ECLKOUT for the ’C6211/C6711 The ’C6211/C6711 has a modified version of the CE space control register, in...
Page 258: Tms320C6211/C6711 Byte Alignment By Endianness
EMIF Registers The read hold and write hold fields have been increased by one bit, to allow greater asynchronous configuration possibilities. The MTYPE field has been increased by one bit to allow for 8-, 16-, and 32-bit interface options for all memory types.
Page 259: Emif Sdram Control Register
The fields in this register are shown in Figure 9–10 and Figure 9–11, and described in Table 9–5. These registers should not be modified while accessing SDRAM. Figure 9–10. TMS320C6201/C6202/C6701 EMIF SDRAM Control Register Reserved SDWID...
Page 260 EMIF Registers Table 9–5. EMIFtoSDRAMControlRegisterFieldDescription Field Description Specifies the t value of the SDRAM / p § – 1 TRC = t Specifies the t value of the SDRAM in CLKOUT2 cycles / p § – 1 TRP = t TRCD Specifies the t value of the SDRAM in CLKOUT2 cycles...
Page 261: Emif Sdram Timing Register
R, +0000 00 ‡ ‡ ‡ RW,+00 R, +0101 1101 1100 RW, +0101 1101 1100 † Applies to TMS320C6201/C6202/C6701 ‡ Applies to TMS320C6211/C6711 only Table 9–6. EMIFSDRAM Timing Register Field Descriptions Field Description † Refresh period in CLKOUT2 cycles PERIOD ‡...
Page 262: Tms320C6211/C6711 Sdram Extension Register
EMIF Registers 9.3.5 TMS320C6211/C6711 SDRAM Extension Register The SDRAM extension register of the ’C6211/C6711 allows programming of many parameters of SDRAM. The programmability offers two distinct advan- tages. First, the ’C6211/C6711 can interface to a wide variety of SDRAMs and is not limited to a few configurations or speed characteristics.
Page 263: Tms320C6211/C6711 Sdram Extension Register Field Descriptions
EMIF Registers Table 9–7. TMS320C6211/C6711 SDRAM Extension Register Field Descriptions Field Description Specified Cas latency of the SDRAM in ECLKOUT cycles TCL = 0: CAS latency = 2 ECLKOUT cycles TCL = 1: CAS latency = 3 ECLKOUT cycles TRAS Specifies t RAS value of the SDRAM in ECLKOUT cycles TRAS = t RAS –...
Page 264: 9.4 Sdram Interface
SDRAM Interface 9.4 SDRAM Interface The TMS320C6201/C6202/C6701 EMIF supports 2-bank, 16M-bit SDRAM and 4 bank, 64M-bit SDRAM, providing an interface to high-speed and high- density memory. The EMIF supports the SDRAM commands shown in Table 9–8. The 16M-bit and 64M-bit SDRAM interfaces are shown in Figure 9–14 and Figure 9–16, respectively.
Page 265: Tms320C6201/C6202/C6701 Emif To 16M-Bit Sdram Interface
SDRAM Interface Figure 9–14. TMS320C6201/C6202/C6701 EMIF to 16M-Bit SDRAM Interface † Clock SDRAS External SDCAS memory 16M-bit SDWE interface SDRAM (EMIF) BE[3:0] DQM[3:0] EA[13] A[11] SDA10 A[10] EA[11:2] A[9:0] ED[31:0] D[31:0] † Clock=SDCLK for ’C6201/C6701. Clock=CLKOUT2 for ’C6202. Figure 9–15. TMS320C6211/C6711 EMIF to 16M-Bit SDRAM Interface...
Page 266: Tms320C6201/C6202/C6701 Emif To 64M-Bit Sdram Interface
SDRAM Interface Figure 9–16. TMS320C6201/C6202/C6701 EMIF to 64M-Bit SDRAM Interface † Clock SDRAS External SDCAS memory 16M-bit SDWE interface SDRAM (EMIF) BE[3:0] DQM[3:0] EA[13] A[11] SDA10 A[10] EA[11:2] A[9:0] ED[31:0] D[31:0] † Clock=SDCLK for ’C6201/C6701. Clock=CLKOUT2 for ’C6202. Table 9–9. TMS320C6201/C6202/C6701 SDRAM Memory Population †...
Page 267: Sdram Control Pins
SDRAM Interface Table 9–10. SDRAM Control Pins SDRAM EMIF Signal Signal SDRAM Function SDA10 Address line A10/autoprecharge disable. Serves as a row address bit during ACTV commands and also disables the autoprecharging function of SDRAM. (’C6201/C6202/C6701 only) SDRAS Row address strobe and command input. Latched by the rising edge of CLK to determine current operation.
Page 268 SDRAM Interface faces. Since the ’C6211/C6711 does not perform background refreshes, all three memory types may be included in the same system. 9-24...
Page 269: Sdram Initialization
SDRAM Interface 9.4.1 SDRAM Initialization The EMIF performs the necessary tasks to initialize SDRAM if any of the CE spaces are configured for SDRAM. An SDRAM initialization is requested by a write of 1 to the INIT bit in the EMIF SDRAM control register. The steps of an initialization are as follows: 1) Send a DCAB command to all CE spaces configured as SDRAM.
Page 270: Sdram Refresh
SDRAM Interface For the ’C6211/C6711, up to four pages of SDRAM can be opened simulta- neously. These pages can be within a single CE space, or spread over all CE spaces. For example, two pages can be open in CE0 and CE2, or four pages can be open in CE0.
Page 271 SDRAM Interface The ’C6201/C6202/C6701 EMIF SDRAM controller prioritizes SDRAM refresh requests with other data access requests posted to it from the EMIF request- ers. The following rules apply: A counter value of 11 invalidates the page information register, forcing the controller to close the current SDRAM page.
Page 272: Mode Register Set
SDRAM Interface For all ’C6000 devices, the EMIF SDRAM interface performs CAS-before- RAS refresh cycles for SDRAM. Some SDRAM manufacturers call this autore- fresh. Prior to an REFR command, a DCAB command is performed to all CE spaces specifying SDRAM to ensure that all active banks are closed. Page in- formation is always invalid before and after a REFR command;...
Page 273: Tms320C6201/C6202/C6701 Mode Register Value
SDA10 EA11 EA10 Write burst Rsvd Rsvd length 0000 Read latency Burst length Table 9–11. TMS320C6201/C6202/C6701 Implied SDRAM Configuration by MRS Value Field Selection Write burst length 1 word Read latency 3 cycles Serial/interleave burst type Serial Burst length 1 word...
Page 274: Tms320C6211/C6711 Mode Register Value (0032H)
SDRAM Interface The ’C6211/C6711 uses a mode register value of either 0032h or 0022h. The register value and description are shown in Figure 9–19 and Figure 9–20. Both values program a default burst length of four words for both reads and writes.
Page 275: Sdram Mode Register Set: Mrs Command
SDRAM Interface Figure 9–21. SDRAM Mode Register Set: MRS Command Clock † BE[3:0] EA[15:2] MRS value SDA10 SDRAS SDCAS SDWE † Clock=SDCLK for ’C6201/C6701. Clock=CLKOUT2 for ’C6202. Clock=ECLKOUT for ’C6211/C6711. External Memory Interface 9-31...
Page 276: Address Shift 9
EA12 is connected directly to A10 signal, instead of using a dedicated pre- charge pin SDA10. Table 9–13. TMS320C6201/C6202/C6701 Byte Address to EA Mapping for SDRAM RAS and CAS EMIF...
Page 277 SDRAM Interface Table 9–14 describes the addressing for a 32-bit wide ’C6211/C6711 SDRAM interface. The address presented on the pins are shifted for 8-bit and 16-bit interfaces. Table 9–14. TMS320C6211/C6711 Byte Address to EA Mapping for 32-bit Interface [21:17] # of column address bits DRAM Cmd Legend:...
Page 278: Timing Requirements
The three programmable values ensure that EMIF control of SDRAM obeys these minimum timing requirements. Consult the SDRAM data sheet for information on the parameters that are appropriate for your particular SDRAM. Table 9–15. TMS320C6201/C6202/C6701 SDRAM Timing Parameters Value in CLKOUT2/ Parameter Description...
Page 279: Sdram Deactivation
SDRAM Interface 9.4.7 SDRAM Deactivation The SDRAM deactivation (DCAB) is performed after a hardware reset or when INIT = 1 in the EMIF SDRAM control register. This cycle is also required by the SDRAMs prior to REFR and MRS. On the ’C6201/C6202/C6701, a DCAB is issued when a page boundary is crossed.
Page 280: Tms320C6211/C6711 Sdram Deac - Deactivate Single Bank
SDRAM Interface The ’C6211/C6711 also supports the DEAC command, whose operation is de- picted in Figure 9–23, which closes a single page of SDRAM specified by the bank select signals. When a page boundary is crossed, the DEAC command is used to close the open page. The ’C6211/C6711 still supports the DCAB command to close all pages prior to REFR and MRS commands.
Page 281: Sdram Read
SDRAM Interface 9.4.8 SDRAM Read 9.4.8.1 TMS320C6201 C6202 C6701 SDRAM Read During an SDRAM read, the selected bank is activated with the row address during the ACTV command. Figure 9–24 shows the timing for the ’C6201/C6202/C6701 issuing three read commands performed at three different column addresses.
Page 282: Tms320C6211 Sdram Read
SDRAM Interface 9.4.8.2 TMS320C6211/C6711 SDRAM Read Figure 9–25 shows the ’C6211/C6711 performing a three word read burst from SDRAM. The ’C6211/C6711 uses a burst length of four, and has a program- mable CAS latency of either two or three cycles. The CAS latency is three cycles in this example (CASL = 1).
Page 283: Sdram Write
If no new access is pending, the DCAB command is not performed until the page information becomes invalid (see section 9.4.2). The values on EA[15:13] during column accesses and the DCAB command are the values latched during the ACTV command. Figure 9–26. TMS320C6201/C6202/C6701 SDRAM Three Word Write Write Write Write Clock †...
Page 284: Tms320C6211/C6711 Sdram Three Word Write
SDRAM Interface 9.4.9.2 TMS320C6211 C6711 SDRAM Write All SDRAM writes have a burst length of four on the ’C6211/C6711. The bank is activated with the row address during the ACTV command. There is no latency on writes, so data is output on the same cycle as the column address. Writes to particular bytes are disabled via the appropriate DQM inputs;...
Page 285: 9.4.10 Tms320C6211/C6711 Seamless Data Access
SDRAM Interface 9.4.10 TMS320C6211/C6711 Seamless Data Access Since the ’C6211/C6711 performs data transfers to SDRAM in bursts of 4 words and can maintain up to 4 open pages in a single CE space, this device is capable of sustaining seamless data transfer to and from multiple pages of SDRAM.
Page 286: Seamless Sdram Write
SDRAM Interface Seamless write transfers are accomplished in the same way. First, bank 0 is opened and after Trcd cycles, the write burst can begin. During the first write burst, a page in bank 1 can be opened. This allows the write to bank 1 to begin immediately after the write burst to bank 0 ends, as shown in Figure 9–29.
Page 287: 9.5 Sbsram Interface
SBSRAM Interface 9.5 SBSRAM Interface As shown in Figure 9–30 (’C6201/C6202/C6701) and Figure 9–31 (’C6211/C6711), the EMIF interfaces directly to industry-standard synchro- nous burst SRAMs (SBSRAMS). This memory interface allows a high-speed memory interface without some of the limitations of SDRAM. Most notably, since SBSRAMs are SRAM devices, random accesses in the same direction can occur in a single cycle.
Page 288: Tms320C6201/C6202/C6701 Sbsram Interface
The SBSRAM interface on the ’C6202 is identical to that of the ’C6201, with the exception that it has been combined with the SDRAM interface. Only one of these two synchronous memory types can be used on a ’C6202 system. Figure 9–30. TMS320C6201/C6202/C6701 SBSRAM Interface † Clock...
Page 289: Sbsram Reads 9
SBSRAM Interface Table 9–17. EMIF SBSRAM Pins EMIF Signal SBSRAM Signal SBSRAM Function SSADS ADSC Address strobe SSOE Output enable SSWE Write enable SSCLK/CLKOUT2/ECLKOUT SBSRAM clock SBSRAMs are latent by their architecture, meaning that read data follows address and control information. Consequently, the EMIF inserts cycles between read and write commands to ensure that no conflict exists on the ED[31:0] bus.
Page 290: Tms320C6211/C6711 Sbsram Six-Word Read
SBSRAM Interface Figure 9–33 shows the timing for ’C6211/C6711 six word read. The address starts with EA[3:2] equal to 10b. A new address is strobed into the SBSRAM on the third cycle to prevent the internal burst counter from rolling over to 000b. The burst is terminated by deasserting the CEn signal while SSADS is strobed low.
Page 291: Sbsram Writes 9
Figure 9–34 shows a four-word write to an SBSRAM. Every access strobes a new address into the SBSRAM. The first access requires an initial start-up pen- alty of two cycles; thereafter, all accesses can occur in a single SSCLK cycle. Figure 9–34. TMS320C6201/C6202/C6701 SBSRAM Four Word Write Write Write...
Page 292: Tms320C6211/C6711 Sbsram Write
SBSRAM Interface Figure 9–35 shows a ’C6211/C6711 six-word write to SBSRAM. The new ad- dress is strobed into SBSRAM on the fifth cycle to prevent the internal burst counter from rolling over to 000b. Figure 9–35. TMS320C6211/C6711 SBSRAM Write Write Write ECLKOUT BE[3:0]...
Page 293: 9.6 Asynchronous Interface
Asynchronous Interface 9.6 Asynchronous Interface The asynchronous interface offers configurable memory cycle types to interface to a variety of memory and peripheral types, including SRAM, EPROM, and flash memory, as well as FPGA and ASIC designs. Table 9–18 lists the asynchronous interface pins. Figure 9–36 shows an interface to standard SRAM, and Figure 9–38, Figure 9–39, and Figure 9–40 show interfaces to 8-, 16-, and 32-bit ROM for the ’C6201/C6202/C6701 and for the ’C6211/C6711 in little-endian mode.
Page 294: Tms6201/C6202/C6701 Emif To 32-Bit Sram Interface
Asynchronous Interface Figure 9–36. TMS6201/C6202/C6701 EMIF to 32-bit SRAM Interface External memory SRAM interface EA[N+2:2] A[N:0] (EMIF) ED[31:0] D[31:0] BE[3:0] UB[1:0], LB[1:0] ARDY Figure 9–37. TMS320C6211/C6711 EMIF to 16-bit SRAM (Big Endian) External clock ECLKIN External memory SRAM interface EA[N+2:2] A[N:0] (EMIF) ED[31:16]...
Page 295: Emif To 8-Bit Rom Interface
Asynchronous Interface Figure 9–38. EMIF to 8-Bit ROM Interface External EA[N+2:2] A[N:0] memory interface ED[7:0] D[7:0] (EMIF) ARDY Figure 9–39. EMIF to 16-Bit ROM Interface External EA[N+2:2] A[N:0] memory interface ED[15:0] D[15:0] (EMIF) ARDY Figure 9–40. EMIF to 32-Bit ROM Interface External EA[N+2:2] A[N:0]...
Page 296: Tms320C6201/C6202/C6701 Rom Modes
Asynchronous Interface 9.6.1 TMS320C6201/C6202/C6701 ROM Modes The EMIF supports 8- and 16-bit-wide ROM access modes which are selected by the MTYPE field in the EMIF CE space control registers. In reading data from these narrow memory spaces, the EMIF packs multiple reads into one 32-bit-wide value.
Page 297: Programmable Asram Parameters
Asynchronous Interface 9.6.1.2 16-Bit ROM Mode In 16-bit ROM mode, the address is left-shifted by 1 to create a half-word address on EA to access 16-bit-wide ROM. The EMIF always packs two consecutive half- words aligned on a 4-byte boundary (byte address = 4N) into a word access. The halfwords are fetched in the following address order: 4N, 4N + 2.
Page 298 Asynchronous Interface 9.6.3 Asynchronous Reads Figure 9–41 show an asynchronous read with the setup, strobe, and hold param- eter programmed with the values 2,3, and 1, respectively. An asynchronous read proceeds as follows: At the beginning of the setup period: CE becomes active.
Page 299: Asynchronous Read Timing Example
Asynchronous Interface Figure 9–41. Asynchronous Read Timing Example Setup Strobe Hold CE Hold CLKOUT1/ ECLKOUT CE† BE[3:0] Address EA[21:2] Read D ED[31:0] ARDY † On the ’C6211/C6711, CE goes high immediately after the programmed hold period. ‡ CLKOUT1 referenced for ’C6201/C6202/C6701, ECLKOUT reference for ’C6211/C6711 External Memory Interface 9-55...
Page 300 Asynchronous Interface 9.6.4 Asynchronous Writes Figure 9–42 shows two back-to-back asynchronous write cycles with the ARDY signal pulled high (always ready). The SETUP, STROBE and HOLD are programmed to 2,3,and 1. At the beginning of the setup period: CE becomes active. BE[3:0] becomes valid.
Page 301: Asynchronous Write Timing Example
Asynchronous Interface Figure 9–42. Asynchronous Write Timing Example Setup Hold Strobe Hold CE write hold Strobe Setup CLKOUT1/ ECLKOUT BE[3:0] EA[21:2] ED[31:0] ARDY † On the ’C6211/C6711, CE goes high immediately after the programmed hold period. ‡ CLKOUT1 referenced for ’C6201/C6202/C6701, ECLKOUT reference for ’C6211/C6711 9.6.5 Ready Input In addition to programmable access shaping, you can insert extra cycles into...
Page 302: Tms320C6201/C6202/C6701 Ready Operation
Asynchronous Interface TMS320C6201/C6202/C6701 Operation: If ARDY is low on the third ris- ing edge of CLKOUT1 before the end of the programmed strobe period, then the strobe period is extended by one CLKOUT1 cycle. For each sub- sequent CLKOUT1 rising edge that ARDY is sampled low, the strobe peri- od is extended by one CLKOUT1 cycle.
Page 303: Tms320C6211/C6711 Ready Operation
Asynchronous Interface TMS320C6211/C6711 Operation: ARDY is sampled for the first time on the ECLKOUT cycle at the end of the programmed strobe period. If sampled low, the strobe period is extended and ARDY is sampled again on the next ECLKOUT cycle. Read data is latched by the ’C6211 on the cycle that ARDY is sampled high.
Page 304 Hold Interface 9.7 Hold Interface The EMIF responds to hold requests for the external bus. The hold handshake allows an external device and the EMIF to share the external bus. The hand- shake mechanism uses two signals: HOLD: hold request input. HOLD is synchronized internally to the CPU clock.
Page 305: Tms320C6201/C6202/C6701 Emif Prioritization Of Requests
EMIF. When the RBTR8 is not set, the current controller is interrupted by a higher priority requester regardless of the number of requests that have occurred. Table 9–20. TMS320C6201/C6202/C6701 EMIF Prioritization of Requests Priority Requestor PRI = 1...
Page 306: Tms320C6211/C6711 Emif Prioritization Of Requests
Memory Request Priority 9.8.2 TMS320C6211/C6711 Memory Request Priority The ’C6211/C6711 has fewer interface requestors because the data memory controller (DMC), program memory controller (PMC), and EDMA transactions are processed by the EDMA. Other requestors include the hold interface and internal EMIF operations, including mode register set (MRS) and refresh (REFR).
Page 307 Boundary Conditions When Writing to EMIF Registers 9.9 Boundary Conditions When Writing to EMIF Registers The EMIF has internal registers that change memory type, asynchronous memory timing, SDRAM refresh, SDRAM initialization (MRS COMMAND), clock speed, arbitration type, HOLD/NOHOLD condition, etc. The following actions can cause improper data reads or writes: Writing to the CE0, CE1, CE2, or CE3 space control registers while an external access to that CE space is active...
Page 308: Power Down
Clock Output Enabling Clock Output Enabling / Emulation Halt Operation / Power Down 9.10 Clock Output Enabling To reduce electromagnetic interference (EMI) radiation, the EMIF allows the disabling (holding high) of CLKOUT2, CLKOUT1, SSCLK, and SDCLK. This disabling is performed by setting the CLK2EN, CLK1EN, SSCEN, and SDCEN bits to 0 in the EMIF global control register, which is shown in Figure 9–6 on page 9-9 and summarized in Table 9–3 on page 9-10.ECLKOUT cannot be disabled using software.
Page 309 Chapter 10 Boot Modes and Configuration This chapter describes the boot modes and device configuration used by the TMS320C6000 platform. It also describes the available boot processes and explains how the device is reset. Topic Page 10.1 Overview ........... . 10-2 10.2 Device Reset .
Page 310: Device Reset
Overview 10.1 Overview The TMS320C6000 platform uses a variety of boot configurations to deter- mine what actions the devices are to perform after reset for proper device init- ialization. Each ‘C6000 device has some or all of the following boot configura- tion options: Selection of the memory map, which determines whether internal or exter- nal memory is mapped at address 0...
Page 311: Boot Configuration Summary
Boot Configuration 10.3 Boot Configuration External pins BOOTMODE[4:0] select the boot configuration. The values of BOOTMODE[4:0] are latched during the low period of RESET. Table 10–1 lists all the values for BOOTMODE[4:0] as well as the associated memory maps and boot processes. For example, the value 00000b on BOOTMODE[4:0] se- lects memory map 0 and indicates that the memory type at address 0 is syn- chronous DRAM organized as four 8-bit-wide banks and that no boot process is selected.
Page 312 Reserved 11111 Reserved The TMS320C6201 and ’C6701 devices latch their boot configuration setting at reset from dedicated BOOTMODE pins. The TMS3206202 latches its boot configuration from five data lines of the ex- pansion bus, XD[4:0]. The XD[4:0] lines directly map to BOOTMODE[4:0], and should be configured using external pull-up and pull-down resistors.
Page 313: Tms320C6211/C6711 Boot Configuration Summary
Table 10–3. They differ in that MAP 0 has external memory mapped at address 0, and MAP 1 has internal memory mapped at address 0. Refer to Chapter 2 and Chapter 3 for program and data memory descriptions. Table 10–3. TMS320C6201/C6701 Memory Map Summary Description of Memory Block in ... Size...
Page 314: Tms320C6202 Memory Map Summary
Boot Configuration The ’C6202 has two memory maps that are supersets of the ’C6201/’C6701 memory maps. All valid ’C6201/’C6701 address ranges are valid on the ’C6202. There are three primary differences: the ’C6202 has larger internal memory spaces, four external memory locations for the expansion bus (XCE[3:0]), and a third serial port.
Page 315: Tms320C6211/C6711 Memory Map Summary
Boot Configuration The ‘C6211 and ’C6711 have only one memory map, which is shown in Table 10–5. Internal memory is always located at address 0, but can be used as both program and data memory. The configuration register for those periph- erals common to the ’C6201, ’C6211, and ’C6711 are located at the same ad- dresses in both processors.
Page 316 Boot Configuration 10.3.2 Memory at Reset Address For ’C6000 processors with multiple memory maps, the boot configuration determines the type of memory located at the reset address for processor operation, address 0 as shown in Table 10–1. When the BOOTMODE [4:0] pins select MAP 1, this memory is internal.
Page 317 Boot Configuration Host boot process: The CPU is held in reset while the remainder of the device is released. During this period, an external host can initialize the CPU’s memory space as necessary through the host interface, including external memory configuration registers. Once the host is finished with all necessary initialization, it must set the DSPINT to complete the boot pro- cess.
Page 318: Dll Multiplier Select
Device Configuration 10.4 Device Configuration Several device settings are configured at reset to determine how the device operates. 10.4.1 Input Clock Mode The on-chip PLL frequency multiplier is configured through static CLKMODE input pins. Different devices in the ’C6000 platform have different numbers of CLKMODE pins.
Page 319 Chapter 11 Multichannel Buffered Serial Ports This chapter describes the operation and hardware of the two multichannel buffered serial ports (McBSPs). It also includes register definitions and timing diagrams for the McBSPs. Topic Page 11.1 Features ........... . 11-2 11.2 McBSP Interface Signals and Registers .
Page 320 Features 11.1 Features The multichannel buffered serial port (McBSP) is based on the standard serial port interface on the TMS320C2x, ’C3x, ’C5x, and ’C54x devices. The McBSP pro- vides: Full-duplex communication Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for receive and transmit Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D and D/A devices...
Page 321: Mcbsp Block Diagram
McBSP Interface Signals and Registers 11.2 McBSP Interface Signals and Registers The multichannel buffered serial port (McBSP) consists of a data path and a control path, which connect to external devices. Data is communicated to these external devices via separate pins for transmission and reception. Con- trol information (clocking and frame synchronization) is communicated via four other pins.
Page 322 McBSP Interface Signals and Registers Data is communicated to devices interfacing to the McBSP via the data transmit (DX) pin for transmission and the data receive (DR) pin for reception. Control information (clocking and frame synchronization) is communicated via CLKX, CLKR, FSX, and FSR.
Page 323: Mcbsp Interface Signals
McBSP Interface Signals and Registers Table 11–1. McBSP Interface Signals I/O/Z Description CLKR I/O/Z Receive clock CLKX I/O/Z Transmit clock CLKS External clock Received serial data Transmitted serial data I/O/Z Receive frame synchronization I/O/Z Transmit frame synchronization Note: I = Input, O = Output, Z = High Impedance Multichannel Buffered Serial Ports 11-5...
Page 324: Mcbsp Registers
McBSP Interface Signals and Registers Table 11–2. McBSP Registers Hex Byte Address § McBSP 0 McBSP 1 McBSP 2 Abbreviation † McBSP Register Name Section – – – Receive buffer register 11.2 – – – Receive shift register 11.2 – –...
Page 325: Mcbsp Cpu Interrupts And Dma Synchronization Events
McBSP Interface Signals and Registers Table 11–4. McBSP CPU Interrupts and DMA Synchronization Events Interrupt Name Description Section RINT Receive interrupt to CPU 11.3.3 XINT Transmit interrupt to CPU 11.3.3 REVT Receive synchronization event to the DMA 11.3.2.1 controller XEVT Transmit synchronization event to the DMA 11.3.2.2 controller...
Page 326: Serial Port Control Register (Spcr)
McBSP Interface Signals and Registers Table 11–5. Serial Port Control Register (SPCR) Field Descriptions Name Function Section FRST Frame sync generator reset 11.5.3 FRST = 0: The frame sync generation logic is reset. Frame sync signal is not generated by the sample rate generator. FRST = 1: Frame sync signal is generated after eight CLKG clocks.
Page 327 McBSP Interface Signals and Registers Table 11–5. Serial Port Control Register (SPCR) Field Descriptions (Continued) Name Function Section RFULL Receive shift register (RSR) full error condition 11.3.7.1 RFULL = 0: Receiver is not in overrun condition. RFULL = 1: DRR is not read, RBR is full, and RSR is full with a new element. RRDY Receiver ready 11.3.2...
Page 328 McBSP Interface Signals and Registers Table 11–5. Serial Port Control Register (SPCR) Field Descriptions (Continued) Name Function Section CLKSTP Clock stop mode 11.7 CLKSTP = 0Xb: Clock stop mode disabled. Normal clocking enabled for non-SPI mode. Clock stop mode enabled for various SPI modes when: CLKSTP = 10b and CLKXP = 0: Clock starts with rising edge without delay.
Page 329: Pin Control Register (Pcr)
McBSP Interface Signals and Registers Figure 11–3.Pin Control Register (PCR) reserved R, +0 15 14 Rsvd XIOEN RIOEN FSXM FSRM CLKXM CLKRM Rsvd CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP R,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW, +0 R,+0 RW,+0 RW,+0 R,+0 RW,+0...
Page 330 McBSP Interface Signals and Registers Table 11–6. Pin Control Register (PCR) Field Descriptions (Continued) Name Function Section CLKRM Receiver clock mode 11.5.2.6 Case 1: Digital loopback mode not set (DLB = 0) in SPCR 11.8 CLKRM = 0: Receive clock (CLKR) is an input driven by an external clock. CLKRM = 1: CLKR is an output pin and is driven by the sample rate generator.
Page 331 McBSP Interface Signals and Registers Table 11–6. Pin Control Register (PCR) Field Descriptions (Continued) Name Function Section CLKXP Transmit clock polarity 11.3.4.1 CLKXP = 0: Transmit data driven on rising edge of CLKX 11.8 CLKXP = 1: Transmit data driven on falling edge of CLKX CLKRP Receive clock polarity 11.3.4.1...
Page 332: Receive Control Register (Rcr)
McBSP Interface Signals and Registers 11.2.2 Receive and Transmit Control Registers: RCR and XCR The receive and transmit control registers (RCR and XCR), shown in Figure 11–4 and Figure 11–5, configure parameters of the receive and transmit operations, respectively. The fields of RCR and XCR are summarized in Figure 11–4.
Page 333: Receive/Transmit Control Register (Rcr/Xcr) Field Descriptions
McBSP Interface Signals and Registers Table 11–7. Receive/Transmit Control Register (RCR/XCR) Field Descriptions Name Function Section RPHASE Receive phases 11.3.4.2 RPHASE = 0: Single phase frame RPHASE = 1: Dual phase frame XPHASE Transmit phases 11.3.4.2 XPHASE = 0: Single phase frame XPHASE = 1: Dual phase frame RFRLEN(1/2) Receive frame length in phase 1 and phase 2...
Page 334 McBSP Interface Signals and Registers Table 11–7. Receive/Transmit Control Register (RCR/XCR) Field Descriptions (Continued) Name Function Section XWDLEN(1/2) Transmit element length in phase 1 and phase 2 11.3.4.5 XWDLEN(1/2) = 000b: 8 bits XWDLEN(1/2) = 001b: 12 bits XWDLEN(1/2) = 010b: 16 bits XWDLEN(1/2) = 011b: 20 bits XWDLEN(1/2) = 100b: 24 bits XWDLEN(1/2) = 101b: 32 bits...
Page 335 McBSP Interface Signals and Registers Table 11–7. Receive/Transmit Control Register (RCR/XCR) Field Descriptions (Continued) Name Function Section RDATDLY Receive data delay 11.3.4.7 RDATDLY = 00b: 0-bit data delay RDATDLY = 01b: 1-bit data delay RDATDLY = 10b: 2-bit data delay RDATDLY = 11b: Reserved XDATDLY Transmit data delay...
Page 336 Data Transmission and Reception 11.3 Data Transmission and Reception As shown in Figure 11–1 on page 11-3, the receive operation is triple-buff- ered and the transmit operation is double-buffered. Receive data arrives on the DR and is shifted into the RSR. Once a full element (8, 12, 16, 20, 24, or 32 bits) is received, the RSR is copied to the receive buffer register (RBR) only if the RBR is not full.
Page 337: Reset State Of Mcbsp Pins
Data Transmission and Reception Table 11–8. Reset State of McBSP Pins McBSP Device Reset Direction McBSP Reset Pins (RESET = 0) Receiver Reset (RRST = 0 and GRST = 1) Input Input CLKR I/O/Z Input Known state if input; CLKR if output I/O/Z Input Known state if input;...
Page 338 Data Transmission and Reception McBSP reset: When the receiver and transmitter reset bits, RRST and XRST, are written with 0, the respective portions of the McBSP are reset and activity in the corresponding section stops. All input-only pins, such as DR and CLKS, and all other pins that are configured as inputs are in a known state.
Page 339 Data Transmission and Reception Alternatively, on either write (steps 1 and 5 above), the transmitter and receiver can be placed in or taken out of reset individually by modifying only the desired bit. The necessary duration of the active(low) period of XRST or RRST is at least two bit clocks (CLKR/CLKX).
Page 340 Data Transmission and Reception data has been read by either the CPU or the DMA controller, RRDY is cleared to 0. Also, at device reset or serial port receiver reset (RRST = 0), the RRDY is cleared to 0 to indicate that no data has yet been received and loaded into DRR.
Page 341: Frame And Clock Operation
Data Transmission and Reception 11.3.4 Frame and Clock Configuration Figure 11–6 shows typical operation of the McBSP clock and frame sync sig- nals. Serial clocks CLKR and CLKX define the boundaries between bits for re- ceive and transmit, respectively. Similarly, frame sync signals FSR and FSX define the beginning of an element transfer.
Page 342 Data Transmission and Reception Figure 11–37 on page 11-53). The receive data arriving at the DR pin is also sampled on the falling edge of CLKR_int. These internal clock signals are either derived from external source via the CLK(R/X) pins or driven by the sample rate generator clock (CLKG) internal to the McBSP.
Page 343: Receive Data Clocking
Data Transmission and Reception In a system where the same clock (internal or external) is used to clock the re- ceiver and transmitter, CLKRP = CLKXP. The receiver uses the opposite edge as the transmitter to ensure valid setup and hold times of data around this edge. Figure 11–7 shows how data clocked by an external serial device using a rising- edge clock can be sampled by the McBSP receiver with the falling edge of the same clock.
Page 344: Dual-Phase Frame Example
Data Transmission and Reception Figure 11–8.Dual-Phase Frame Example Phase 1 Phase 2 Phase 2 Phase 1 Phase 2 Element 3 Element 1 Element 1 Element 2 Element 2 CLK(R/X) FS(R/X) D(R/X) Table 11–9. RCR/XCR Fields Controlling Elements per Frame and Bits per Element RCR/XCR field Control Serial Port Serial Port...
Page 345: Inter-Ic Sound (Iis) Timing
Data Transmission and Reception Figure 11–9.Inter-IC Sound (IIS) Timing Phase 1 Phase 2 CLK(R/X) FPER FWID FS(R/X) D(R/X) 11.3.4.4 Frame Length: (R/X)FRLEN(1/2) Frame length can be defined as the number of serial elements transferred per frame. The length corresponds to the number of elements or logical time slots or channels per frame synchronization signal.
Page 346: Mcbsp Receive/Transmit Element Length Configuration
Data Transmission and Reception 11.3.4.5 Element Length: (R/X)WDLEN(1/2) The (R/X)WDLEN(1/2) fields in the receive/transmit control register determine the element length in bits per element for the receiver and the transmitter for each phase of the frame, as indicated in Table 11–9. Table 11–11 shows how the value of these fields selects particular element lengths in bits.
Page 347: Single-Phase Frame Of Four 8-Bit Elements
Data Transmission and Reception Figure 11–10. Single-Phase Frame of Four 8-Bit Elements Element 1 Element 3 Element 2 Element 4 CLKR RBR-to-DRR copy RBR–to–DRR copy RBR-to-DRR copy RBR–to-DRR copy CLKX DXR-to-XSR copy DXR-to-XSR copy DXR-to-XSR copy DXR-to-XSR copy The example in Figure 11–10 can also be viewed as a data stream of a single- phase frame of one 32-bit data element, as shown in Figure 11–11.
Page 348 Data Transmission and Reception 11.3.4.7 Data Delay: (R/X)DATDLY The start of a frame is defined by the first clock cycle in which frame synchro- nization is active. The beginning of actual data reception or transmission with respect to the start of the frame can be delayed if required. This delay is called data delay.
Page 349 Data Transmission and Reception Another common operation uses a data delay of 2. This configuration allows the serial port to interface to different types of T1 framing devices in which the data stream is preceded by a framing bit. During the reception of such a stream with a data delay of two bits, the framing bit appears after a 1-bit delay and data ap- pears after a 2-bit delay).
Page 350 Data Transmission and Reception 11.3.4.8 Multiphase Frame Example: AC97 Figure 11–14 shows an example of the Audio Codec ’97 (AC97) standard, which uses the dual-phase frame feature. The first phase consists of a single 16-bit element. The second phase consists of 12 20-bit elements. The phases are configured as follows: (R/X)PHASE = 1b: specifying a dual-phase frame (R/X)FRLEN1 = 0b: specifying one element per frame in phase 1...
Page 351 Data Transmission and Reception Figure 11–15. AC97 Bit Timing Near Frame Synchronization CLKR 1-bit data delay P2E12B1 P2E12B0 P1E1B15 P1E1B14 P1E1B13 P1E1B12 † PxEyBz denotes phase x, element y, and bit z. 11.3.5 McBSP Standard Operation During a serial transfer, there are typically periods of serial port inactivity between packets or transfers.
Page 352: Receive Operation
Data Transmission and Reception Figure 11–16. McBSP Standard Operation CLK(R/X) FS(R/X) D(R/X) Receive Operation 11.3.5.1 Figure 11–17 shows serial reception. Once the receive frame synchronization signal (FSR) transitions to its active state, it is detected on the first falling edge of the receiver’s CLKR.
Page 353 Data Transmission and Reception Figure 11–18. Transmit Operation CLKX XRDY DXR to XSR copy Write of DXR DXR to XSR copy Write of DXR 11.3.5.3 Maximum Frame Frequency The frame frequency is determined by the following equation, which calculates the period between frame synchronization signals: it clock frequency Frame frequency Number of bit clocks between frame sync signals...
Page 354 Data Transmission and Reception Figure 11–19. Maximum Frame Frequency Transmit and Receive CLK(R/X) FS(R/X) D(R/X) Note: For (R/X)DATDLY = 0, the first bit of data transmitted is asynchronous to CLKX, as shown in Figure 11–12. 11.3.6 Frame Synchronization Ignore The McBSP can be configured to ignore transmit and receive frame synchro- nization pulses.
Page 355 Data Transmission and Reception 11.3.6.1 Frame Sync Ignore and Unexpected Frame Sync Pulses RFIG and XFIG are used to ignore unexpected frame sync pulses. Any frame sync pulse is considered unexpected if it occurs one or more bit clocks earlier than the programmed data delay from the end of the previous frame specified by ((R/X)DATDLY).
Page 356 Data Transmission and Reception Figure 11–21 shows McBSP operation when unexpected frame synchronization signals are ignored by setting (R/X)FIG = 1. Here, the transfer of element B is not affected by an unexpected frame synchronization. Figure 11–21. Unexpected Frame Synchronization With (R/X)FIG = 1 CLK(R/X) Frame synchronization ignored FS(R/X)
Page 357 Data Transmission and Reception 11.3.6.2 Data Packing using Frame Sync Ignore Bits Section 11.3.4.6 describes one method of changing the element length and frame length to simulate 32-bit serial element transfers, thus requiring much less bus bandwidth than four 8-bit transfers require. This example works when there are multiple elements per frame.
Page 358 Data Transmission and Reception Figure 11–23. Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 Element 1 CLKR Frame ignored Frame ignored Frame ignored RBR-to-DRR copy CLKX Frame ignored Frame ignored Frame ignored DXR-to-XSR copy 11-40...
Page 359 Data Transmission and Reception 11.3.7 Serial Port Exception Conditions There are five serial port events that can constitute a system error: Receive overrun (RFULL = 1) Unexpected receive frame synchronization (RSYNCERR = 1) Transmit data overwrite Transmit empty (XEMPTY = 0) Unexpected transmit frame synchronization (XSYNCERR = 1) 11.3.7.1 Reception With Overrun: RFULL RFULL = 1 in the SPCR indicates that the receiver has experienced overrun...
Page 360 Data Transmission and Reception yet. Another element, C, arrives and fills RSR. DRR is finally read, but not earli- er than two and one half cycles before the end of element C. New data D over- writes the previous element C in RSR. If RFULL is still set after the DRR is read, the next element can overwrite D if DRR is not read in time.
Page 361 Data Transmission and Reception 11.3.7.2 Unexpected Receive Frame Synchronization: RSYNCERR Figure 11–26 shows the decision tree that the receiver uses to handle all incom- ing frame synchronization pulses. The diagram assumes that the receiver has been activated (RRST = 1). Unexpected frame sync pulses can originate from an external source or from the internal sample rate generator.
Page 362 Data Transmission and Reception Figure 11–26. Decision Tree Response to Receive Frame Synchronization Pulse Receive frame sync pulse occurs Case 2: Unexpected Normal reception frame sync pulse ? Start receiving data Case 3: RFIG = 1 ? Abort reception. Set RSYNCERR. Start next reception.
Page 363 Data Transmission and Reception 11.3.7.3 Transmit With Data Overwrite Figure 11–28 shows what happens if the data in DXR is overwritten before it is transmitted. Suppose you load the DXR with data C. A subsequent write to the DXR overwrites C with D before C is copied to the XSR. Thus, C is never trans- mitted on DX.
Page 364 Data Transmission and Reception When the transmitter is taken out of reset (XRST = 1), it is in a transmit ready (XRDY = 1) and transmit empty (XEMPTY = 0) condition. If DXR is loaded by the CPU or the DMA controller before FSX goes active, a valid DXR-to-XSR transfer occurs.
Page 365 Data Transmission and Reception 11.3.7.5 Unexpected Transmit Frame Synchronization: XSYNCERR Figure 11–26 shows the decision tree that the transmitter uses to handle all incoming frame synchronization signals. The diagram assumes that the trans- mitter has been started (XRST = 1). An unexpected transmit frame sync pulse is defined as a sync pulse that occurs XDATDLY bit clocks earlier than the last transmitted bit of the previous frame.
Page 366 Data Transmission and Reception Case 3: Unexpected transmit frame synchronization with XFIG = 0. The case for frame synchronization with XFIG = 0 at maximum packet frequen- cy is shown in Figure 11–20. Figure 11–32 shows the case for normal op- eration of the serial port with interpacket intervals.
Page 367 Data Transmission and Reception 11.3.8 Receive Data Justification and Sign Extension: RJUST RJUST in the SPCR selects whether data in the RBR is right- or left-justified (with respect to the MSB) in the DRR. If right justification is selected, RJUST further selects whether the data is sign-extended or zero-filled.
Page 368 µ -LAW/A-LAW Companding Hardware Operation m-LAW/A-LAW Companding Hardware Operation 11.4 µ-LAW/A-LAW Companding Hardware Operation Companding ( com pressing and ex panding ) hardware allows compression and expansion of data in either µ-law or A-law format. The specification for µ-law and A-law log PCM is part of the CCITT G.711 recommendation. The companding standard employed in the United States and Japan is µ-law and allows 14 bits of dynamic range.
Page 369 µ -LAW/A-LAW Companding Hardware Operation m-LAW/A-LAW Companding Hardware Operation Figure 11–34. Companding Data Formats LAW16 µ-Law Value LAW16 Value A-law Figure 11–35. Transmit Data Companding Format in DXR DXR bits Don’t care LAW16 For reception, the 8-bit compressed data in RBR is expanded to a left-justified 16-bit data, LAW16.
Page 370 µ -LAW/A-LAW Companding Hardware Operation m-LAW/A-LAW Companding Hardware Operation Figure 11–36 shows two methods by which the McBSP can compand internal data. Data paths for these two methods are indicated by (DLB) and (non-DLB) arrows. Non-DLB: When both the transmit and receive sections of the serial port are reset, the DRR and DXR are internally connected through the com- panding logic.
Page 371 Programmable Clock and Framing 11.5 Programmable Clock and Framing The McBSP has several means of selecting clocking and framing for both the receiver and transmitter. Clocking and framing can be sent to both portions by the sample rate generator. Each portion can select external clocking and/or framing independently.
Page 372 Programmable Clock and Framing 11.5.1 Sample Rate Generator Clocking and Framing The sample rate generator is composed of a 3-stage clock divider that provides a programmable data clock (CLKG) and framing signal (FSG), as shown in Figure 11–38. CLKG and FSG are McBSP internal signals that can be pro- grammed to drive receive and/or transmit clocking, CLK(R/X), and framing, FS(R/X).
Page 373 Programmable Clock and Framing 11.5.1.1 Sample Rate Generator Register (SRGR) The sample rate generator register (SRGR) shown in Figure 11–39 and summarized in Table 11–14, controls the operation of various features of the sample rate generator. This section describes the fields in the SRGR. Figure 11–39.
Page 374 Programmable Clock and Framing Table 11–14. Sample Rate Generator Register (SRGR) Field Summary (Continued) Name Function Section FPER Frame period. This field’s value plus 1 determines when the next frame sync signal 11.5.3.1 should become active. Valid values: 0 to 4095 FWID Frame width.
Page 375 Programmable Clock and Framing 11.5.2 Data Clock Generation When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1), the data clocks (CLK(R/X)) are driven by the internal sample rate generator output clock, CLKG. You can select for the receiver and transmitter from a variety of data bit clocks including: The input clock to the sample rate generator, which can be either the inter- nal clock source or a dedicated external clock source (CLKS).
Page 376 Programmable Clock and Framing 11.5.2.3 Bit Clock Polarity: CLKSP The external clock (CLKS) is selected to drive the sample rate generator clock divider by selecting CLKSM = 0. In this case, the CLKSP bit in the SRGR selects the edge of CLKS on which sample rate generator data bit clock (CLKG) and frame sync signal (FSG) are generated.
Page 377 Programmable Clock and Framing Figure 11–40. CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 CLKS (CLKSP = 1) CLKS (CLKSP = 0) FSR external (FSRP = 0) FSR external (FSRP = 1) CLKG (no need to resync) CLKG (needs resync) Figure 11–41.
Page 378 Programmable Clock and Framing These figures show what happens to CLKG when it is initially in sync and GSYNC = 1, as well as when it is not in sync with the frame synchronization and GSYNC = 1. When GSYNC = 1, the transmitter can operate synchronously with the receiv- er, provided that the following conditions are met: FSX is programmed to be driven by the sample rate generator frame sync, FSG (FSGM = 1 in the SRGR and FSXM = 1 in the PCR).
Page 379 Programmable Clock and Framing 11.5.2.7 Transmit Clock Selection: CLKXM Table 11–16 shows how the CLKXM bit in the PCR selects the transmit clock and whether the CLKX pin is an input or output. Table 11–16. Transmit Clock Selection CLKXM Source of Transmit Clock CLKX Function in PCR The external clock drives the CLKX input pin.
Page 380 Programmable Clock and Framing 11.5.3.1 Frame Period and Frame Width: FPER and FWID The FPER block is a 12-bit down counter that can count down the generated data clocks from 4095 to 0. FPER controls the period of active frame sync pulses.
Page 381 Programmable Clock and Framing Table 11–17. Receive Frame Synchronization Selection GSYNC Source of Receive Frame FSR Pin Function in SPCR in PCR in SRGR Synchronization External frame sync signal drives Input the FSR input pin, whose signal is then inverted as determined by FSRP before being used as FSR_int.
Page 382 Programmable Clock and Framing Table 11–18. Transmit Frame Synchronization Selection FSXM FSGM Source of Transmit Frame FSX Pin Function in PCR in SRGR Synchronization External frame sync input on the FSX Input pin. This is inverted by FSXP before be- ing used as FSX_int.
Page 383 Programmable Clock and Framing 11.5.4 Clocking Examples 11.5.4.1 Double-Rate ST-BUS Clock Figure 11–43 shows the McBSP timing to be compatible with the Mitel ST- Bus . The operation is running at maximum frame frequency. CLK(R/X)M = 1: CLK(R/X)_int generated internally by sample rate generator GSYNC = 1: CLKG is synchronized with the external frame sync signal in- put on FSR.
Page 384 Programmable Clock and Framing 11.5.4.2 Single-Rate ST-BUS Clock This example is the same as the ST-BUS example except for the following items: CLKGDV = 0: CLKS drives CLK(R/X)_int without any divide down (single- rate clock). CLKSP = 0: The rising edge of CLKS generates internal clocks CLKG and CLK(R/X)_int.
Page 385 Programmable Clock and Framing 11.5.4.3 Double-Rate Clock This example is the same as the ST-BUS example except for the following: CLKSP = 0: The rising edge of CLKS generates CLKG and CLK(R/X). CLKGDV = 1: CLKG, CLKR_int, and CLKX_int frequencies are half of the CLKS frequency.
Page 386 Multichannel Selection Operation 11.6 Multichannel Selection Operation Multiple channels can be independently selected for the transmitter and receiver by configuring the McBSP with a single-phase frame. Each frame represents a time-division multiplexed data stream. The number of elements per frame repre- sented by (R/X)FRLEN1 denotes the number of channels available for selection.
Page 387 Multichannel Selection Operation Figure 11–46. Multichannel Control Register rsvd XPBBLK XPABLK XCBLK XMCM R, +0000 000 RW, +00 RW, +00 R, +000 RW, +00 rsvd RPBBLK RPABLK RCBLK rsvd RMCM R, +0000 000 RW, +00 RW, +00 R, +000 R, +0 RW, +0 Table 11–19.
Page 388 Multichannel Selection Operation Table 11–19. Multichannel Control Register Field Descriptions (Continued) Name Function Section RCBLK Receive current subframe 11.6.3.2 RCBLK = 000b: Subframe 0. Element 0 to element 15 RCBLK = 001b: Subframe 1. Element 16 to element 31 RCBLK = 010b: Subframe 2. Element 32 to element 47 RCBLK = 011b: Subframe 3.
Page 389 Multichannel Selection Operation Table 11–19. Multichannel Control Register Field Descriptions (Continued) Name Function Section RPABLK Receive partition A subframe 11.6.3 RPABLK = 00b: Subframe 0. Element 0 to element 15 RPABLK = 01b: Subframe 2. Element 32 to element 47 RPABLK = 10b: Subframe 4.
Page 390 Multichannel Selection Operation Figure 11–47. Element Enabling by Subframes in Partitions A and B Subframe # (R/X)PABLK Partition A 0–15 32–47 64–79 96–111 0–15 elements (R/X)PBBLK Partition B 16–31 48–63 80–95 112–127 elements FS(R/X) Transmit data masking allows an element enabled for transmit to have its DX pin set to the high-impedance state during its transmit period.
Page 391 Multichannel Selection Operation XMCM = 11b: In this mode, symmetric transmit and receive operation is forced. Symmetric operation occurs when a device transmits and receives on the same set of subframes. These subframes are determined by setting RP(A/B)BLK. The elements in each of these subframes can then be en- abled/selected using the RCER register for receive.
Page 392 Multichannel Selection Operation Figure 11–48. XMCM Operation (a) XMCM = 00b XRDY DXR-to-XSR copy (E3) Write of DXR DXR-to-XSR copy Write of DXR (E1) (E1) (E3) DXR to XSR Write of DXR DXR-to-XSR copy (E0) (E2) (E2) (b) XMCM = 01b, XPABLK = 00b, XCER = 1010b XRDY DXR-to-XSR copy (E3) Write of DXR (E3)
Page 393 Multichannel Selection Operation Figure 11–48. XMCM Operation (Continued) (c) XMCM = 10b, XPABLK = 00b, XCER = 1010b XRDY DXR-to-XSR copy (E3) DXR-to-XSR copy Write of DXR Write of DXR (E1) (E3) (E1) DXR to XSR Write of DXR DXR-to-XSR copy (E0) (E2) (E2)
Page 394 Multichannel Selection Operation 11.6.3.1 Channel Enable Registers: (R/X)CER The receive channel enable register (RCER) and transmit channel enable regis- ter (XCER) are used to enable any of the 32 elements for receive and transmit, respectively. Of the 32 elements, 16 belong to a subframe in partition A and the other 16 belong to a subframe in partition B.
Page 395 Multichannel Selection Operation Table 11–20. Receive/Transmit Channel Enable Register Field Description Name Function RCEA n Receive channel enable RCEA n = 0: Disables reception of the n th element in an even-numbered subframe in partition A RCEA n = 1: Enables reception of the n th element in an even-numbered subframe in partition A XCEA n Transmit channel enable XCEA n = 0: Disables transmission of the n th element in an even-numbered subframe in...
Page 396 Multichannel Selection Operation 11.6.3.3 End-of-Subframe Interrupt At the end of every subframe (16 elements or less) boundary during multichan- nel operation, the receive interrupt (RINT) or transmit interrupt (XINT) to the CPU is generated if RINTM = 01b or XINTM = 01b in the SPCR, respectively. This interrupt indicates that a new partition has been crossed.
Page 397 Multichannel Selection Operation In the case when two McBSPs are used to transmit data over the same TDM line, bus contention occurs if DXENA = 0. The first McBSP turns off the transmission of the last data bit (changes DX from valid to Hi–Z) after a disable time specified in the datasheet.
Page 398 SPI Protocol: CLKSTP 11.7 SPI Protocol: CLKSTP A system conforming to this protocol has a master-slave configuration. The SPI protocol is a 4-wire interface composed of serial data in (master in slave out or MISO), serial data out (master out slave in or MOSI), shift clock (SCK), and an active (low) slave enable (SS) signal.
Page 399 SPI Protocol: CLKSTP Figure 11–53. SPI Configuration: McBSP as the Slave SPI compliant McBSP slave master CLKX MISO MOSI The clock stop mode (CLKSTP) of the McBSP provides compatibility with the SPI protocol. The McBSP supports two SPI transfer formats which are specified by the clock stop mode field (CLKSTP) in the SPCR.
Page 400 SPI Protocol: CLKSTP Figure 11–54. SPI Transfer with CLKSTP = 10b CLKX (CLKXP=0)/SCK CLKX (CLKXP=1)/SCK D(R/X)/MOSI (from master) † D(R/X)/MISO (from slave) § FSX/SS Figure 11–55. SPI Transfer with CLKSTP = 11b CLKX (CLKXP=0)/SCK CLKX (CLKXP=1)/SCK D(R/X)/MOSI (from master) † D(R/X)/MISO (from slave) §...
Page 401 SPI Protocol: CLKSTP Figure 11–54 is the timing diagram when CLKSTP = 10b. In this SPI transfer format, the transition of the first clock edge (CLKX) marks the beginning of data transfer, provided the slave enable (FSX/SS) is already asserted. Data trans- fer is synchronized to the first clock edge.
Page 402 SPI Protocol: CLKSTP 11.7.1 McBSP Operation as the SPI Master When the McBSP is the SPI master, it generates the master clock CLKX and the slave enable FSX. Therefore, CLKX should be configured as an output (CLKXM = 1) and FSX should be configured as an output that can be con- nected to the slave enable (SS) input on the slave device (FSXM = 1).
Page 403 SPI Protocol: CLKSTP 11.7.2 McBSP Operation as the SPI Slave When the McBSP is an SPI slave device, the master clock CLKX and slave enable FSX are generated by an external SPI master, as shown in Figure 11–53. Thus, the CLKX and FSX pins are configured as inputs by set- ting the CLKXM and FSXM fields to zero in the PCR.
Page 404 SPI Protocol: CLKSTP 11.7.3 McBSP Initialization for SPI Mode The operation of the serial port during device reset, transmitter reset, and receiver reset is described in section 11.3.1. For McBSP operation as a master or a slave in SPI mode, you must follow these steps for proper initialization: 1) Set XRST = RRST = 0 in SPCR.
Page 405 McBSP Pins as General-Purpose I/O 11.8 McBSP Pins as General-Purpose I/O Two conditions allow the serial port pins (CLKX, FSX, DX, CLKR, FSR, DR, and CLKS) to be used as general-purpose I/O rather than serial port pins: The related portion (transmitter or receiver) of the serial port is in reset: (R/X)RST = 0 in the SPCR General-purpose I/O is enabled for the related portion of the serial port: (R/X)IOEN = 1 in the PCR...
Page 406 Chapter 12 Timers This chapter describes the 32-bit timer functionality, registers, and signals. Topic Page 12.1 Overview ........... . 12-2 12.2 Timer Registers .
Page 407 Overview Overview 12.1 The device has two 32-bit general-purpose timers that you can use to: Time events Count events Generate pulses Interrupt the CPU Send synchronization events to the DMA The timers have two signaling modes and can be clocked by an internal or an external source.
Page 408 Overview Figure 12–1. Timer Block Diagram Peripheral Bus to CPU and DMA Count Count enable zero Timer counter register Timer period Edge detect register CLKSRC Equals comparator (CPU clock)1/4 Pulse generator PWID TSTAT, timer output TINT, timer interrupt to CPU and DMA INVOUT INVINP DATIN...
Page 409: Timer Registers
Timer Registers 12.2 Timer Registers Table 12–1 describes the three registers that configure timer operation. Table 12–1. Timer Registers Hex Byte Address Timer 0 Timer 1 Name Description Section 01940000 01980000 Timer Control Determines the operating mode of the timer, monitors 12.2.1 the timer status, and controls the function of the TOUT pin.
Page 410 Timer Registers Table 12–2. Timer Control Register Field Descriptions (Continued) Bitfield Description Section Hold. Counter may be read or written regardless of HLD value. 12.3 HLD = 0: Counter is disabled and held in the current state. HLD = 1: Counter is allowed to count. Clock/pulse mode 12.6 C/P = 0: Pulse mode.
Page 411 Timer Registers 12.2.2 Timer Period Register The timer period register (Figure 12–3) contains the number of timer input clock cycles to count. This number controls the frequency of TSTAT. Figure 12–3. Timer Period Register Timer Period RW, +0 12.2.3 Timer Counter Register The timer counter register (Figure 12–4) increments when it is enabled to count.
Page 412 Resetting the Timers and Enabling Counting: GO and HLD 12.3 Resetting the Timers and Enabling Counting: GO and HLD Table 12–3 shows how the GO and HLD enable basic features of timer operation. Table 12–3. Timer GO and HLD Field Operation Operation Description Holding the timer...
Page 413 Timer Counting Timer Counting / Timer Clock Source Selection: CLKSRC 12.4 Timer Counting The timer counter runs at the CPU clock rate. However, counting is enabled on the low-to-high transition of the timer count enable source. This transition is detected by the edge detect circuit shown in Figure 12–1. Each time an ac- tive transition is detected, one CPU-clock-wide clock enable pulse is gener- ated.
Page 414 Timer Pulse Generation 12.6 Timer Pulse Generation The two basic pulse generation modes are pulse mode and clock mode, as shown in Figure 12–5 and Figure 12–6, respectively. You can select the mode with the C/P bit of the timer control register. Note that in pulse mode, PWID in the timer control register can set the pulse width to either one or two input clock periods.
Page 415 Timer Pulse Generation Table 12–4. TSTAT Parameters in Pulse and Clock Modes Mode Frequency Period Width High Width Low f (clock source) timer period register (PWID + 1) timer period register – (PWID + 1) Pulse Pulse timer period register f (clock source) f (clock source) f (clock source)
Page 416: Timer Interrupts
Boundary Conditions in the Control Registers / Timer Interrupts / Emulation Operation Boundary Conditions in the Control Registers 12.7 Boundary Conditions in the Control Registers The following boundary conditions affect timer operation: 1) Timer period and counter register value is 0: After device reset and before the timer starts counting, TSTAT is held at 0.
Page 417 Chapter 13 Interrupt Selector and External Interrupts This chapter describes the interrupt selector and registers available. Topic Page 13.1 Available Interrupt Sources ........13-2 13.2 External Interrupt Signal Timing .
Page 418 Available Interrupt Sources 13.1 Available Interrupt Sources The ‘C6000 peripheral set has up to 32 interrupt sources. The CPU however has 12 interrupts available for use. The interrupt selector allows you to choose and prioritize which 12 of the 32 your system needs to use. The interrupt selec- tor also allows you to effectively change the polarity of external interrupt inputs.
Page 419 Available Interrupt Sources Table 13–1. TMS320C6201/C6202/C6701 Available Interrupts Interrupt Interrupt Interrupt Description Selection Number Acronym 00000b DSPINT Host processor to DSP interrupt 00001b TINT0 Timer 0 interrupt 00010b TINT1 Timer 1 interrupt 00011b SD_INT EMIF SDRAM timer interrupt 00100b EXT_INT4...
Page 420 Available Interrupt Sources The EDMA controller in the ‘C6211/C6711 device has 16 channels; each trig- gered by a specific event. As in the other ’C6000 platform of devices, the ’C6211/C6711 CPU has 12 interrupts available for use. Although there is provi- sion for 32 interrupt sources, the ‘C6211/C6711 provides for 13 interrupt sources.
Page 421 External Interrupt Signal Timing 13.2 External Interrupt Signal Timing EXT_INT4–7, and NMI are dedicated external interrupt sources. In addition, the FSR and FSX can be programmed to directly drive the RINT and XINT signals. Because these signals are asynchronous, they are passed through two regis- ters before being sent to either the DMA or CPU.
Page 422 External Interrupt Signal Timing Figure 13–1. Timing of External Interrupt Related Signals CLKOUT1 CLKOUT2 2–3 CLKOUT1 EXT_INT4 pin CLKOUT1 INT4_int IACK_int 0100 INUM_int CLKOUT 2 2X CLKOUT 2 IACK pin 4X CLKOUT 2 0100 INUM pins 13-6...
Page 423 Interrupt Selector Registers 13.3 Interrupt Selector Registers Table 13–3 shows the interrupt selector registers. The interrupt multiplexer registers determine the mapping between the interrupt sources in Table 13–1 and the CPU interrupts 4 through 15 (INT4–INT15). The external interrupt polarity register sets the polarity of external interrupts. Table 13–3.
Page 424 Interrupt Selector Registers 13.3.2 Interrupt Multiplexer Register The INTSEL fields in the interrupt multiplexer registers, shown in Figure 13–3 and Figure 13–4 allow mapping the interrupt sources in to particular interrupts. The INTSEL4–INTSEL15 correspond to CPU interrupts INT4–INT15. By setting the INTSEL fields to the value of the desired interrupt selection number in Table 13–1 or Table 13–2, you may map any interrupt source to any CPU interrupt.
Page 425 Interrupt Selector Registers Table 13–4. Default Interrupt Mapping Related INTSEL Interrupt Interrupt Description Interrupt INTSEL field Reset Value Acronym INT4 INTSEL4 00100b EXT_INT4 External interrupt pin 4 INT5 INTSEL5 00101b EXT_INT5 External interrupt pin 5 INT6 INTSEL6 00110b EXT_INT6 External interrupt pin 6 INT7 INTSEL7 00111b...
Page 426 Configuring the Interrupt Selector 13.4 Configuring the Interrupt Selector The interrupt selector registers are meant to be configured once after reset dur- ing initialization and before enabling interrupts. Note: Once the registers have been set, the interrupt flag register should be cleared by the user after some delay to remove any spurious transitions caused by the configuration.
Page 427 Chapter 14 Power-Down Logic This chapter describes the power-down modes. Topic Page 14.1 Overview ........... . 14-2 14.2 Triggering, Wake-Up, and Effects .
Page 428 Overview 14.1 Overview Most of the operating power of CMOS logic is dissipated during circuit switching from one logic state to another. By preventing some or all of chip’s logic from switching, significant power savings can be realized without losing any data or operational context.
Page 429 Overview Figure 14–1. Power-Down Mode Logic CLKOUT1 TMS320C6201/TMS320C6701 Internal clock tree Power- Clock Internal Internal down peripheral peripheral logic PWRD C6200 CPU CLKIN RESET Figure 14–2. PWRD Field of the CSR Register 31 16 Enabled Enabled rsvd interrupt non-enabled wake interrupt wake Table 14–1.
Page 430 Triggering, Wake-Up, and Effects 14.2 Triggering, Wake-Up, and Effects Power-down mode PD1 takes effect eight to nine clock cycles after the instruc- tion that caused the power down (by setting the idle bits in the CSR). Use the following code segment to enter power down: B NextInst ;branch does not effect program flow, but hides the move to the CSR in the delay...
Page 431 Triggering, Wake-Up, and Effects Table 14–2. Characteristics of the Power-Down Modes Power-Down Trigger Action Wake-up Method Effect on Chip’s Operation Mode write logic 001001b internal interrupt, CPU halted (except for the interrupt logic) or 010001b to bits external interrupt or 15-10 of the CSR Reset write logic 011010b to...
Page 432 Additional Power-Saving Modes for the TMS320C6202 14.3 Additional Power-Saving Modes for the TMS320C6202 In addition to the power down modes common to all of the C6x devices, the ’C6202 has the ability to turn off clocks to individual peripherals on the device. This feature allows the user to selectively turn off peripherals which are not be- ing used for a specific application and not pay the extra price in power con- sumption for unused peripherals.
Page 433 Additional Power-Saving Modes for the TMS320C6202 Table 14–4 lists and describes the fields in the TMS320C6202 peripheral power-down memory-mapped register. Table 14–4. Description of TMS320C6202 Power-Down Control Fields Field Description Section PDDMA Enable/disable internal DMA clock 14.3 PDDMA=0: internal DMA clock allowed to clock PDDMA=1: internal DMA clock disabled.
Page 434 Additional Power-Saving Modes for the TMS320C6202 You must careful to not disable a portion of the device which is being used, since the peripheral in question will not be operational. A clock-off mode can be entered and exited depending on the needs of the application. For example, if an application does not need the serial ports, the ports can be disabled and then re-enabled when needed.
Page 435 Chapter 15 Designing for JTAG Emulation This chapter assists you in meeting the design requirements of the XDS510 emulator with respect to JTAG designs and discusses the XDS510 cable (manufacturing part number 2617698-0001). This cable is identified by a label on the cable pod marked JTAG 3/5V and supports both standard 3-volt and 5-volt target system power inputs.
Page 436 Designing Your Target System’s Emulator Connector (14-Pin Header) 15.1 Designing Your Target System’s Emulator Connector (14-Pin Header) JTAG target devices support emulation through a dedicated emulation port. This port is a superset of the IEEE 1149.1 standard and is accessed by the emulator.
Page 437 Designing Your Target System’s Emulator Connector (14-Pin Header) / Bus Protocol / IEEE 1149.1 Standard Designing Your Target System’s Emulator Connector (14-Pin Header) Although you can use other headers, recommended parts include: straight header, unshrouded DuPont Connector Systems part numbers: 65610–114 65611–114 67996–114...
Page 438 JTAG Emulator Cable Pod Logic 15.4 JTAG Emulator Cable Pod Logic Figure 15–2 shows a portion of the emulator cable pod. These are the func- tional features of the pod: Signals TDO and TCK_RET can be parallel-terminated inside the pod if required by the application.
Page 439 These timing parameters are calculated from values specified in the standard data sheets for the emulator and cable pod and are for reference only. Texas Instruments does not test or guarantee these timings. The emulator pod uses TCK_RET as its clock source for internal synchroni- zation.
Page 440 Emulation Timing Calculations 15.6 Emulation Timing Calculations The following examples help you calculate emulation timings in your system. For actual target timing parameters, see the appropriate device data sheets. Assumptions: Target TMS/TDI setup to TCK high 10 ns su(TTMS) Target TDO delay from TCK low 15 ns d(TTDO) Target buffer delay, maximum...
Page 441 Emulation Timing Calculations Case 2: Single/multiprocessor, TMS/TDI/TCK buffered input, TDO buffered output, TMS/TDI timed from TCK_RET low. d (TMSmax su (TTMS (bufskew) pd (TCK_RET–TMS TDI) TCKfactor 20ns 10ns 1.35 ns + 78.4ns (12.7 MHz) d (TTDO su (TDOmin) d (bufmax pd (TCK_RET–TDO) TCKfactor [15ns...
Page 442 Connections Between the Emulator and the Target System 15.7 Connections Between the Emulator and the Target System It is extremely important to provide high-quality signals between the emulator and the JTAG target system. Depending upon the situation, you must supply the correct signal buffering, test clock inputs, and multiple processor intercon- nections to ensure proper emulator and target system operation.
Page 443 Connections Between the Emulator and the Target System Buffered transmission signals. In this situation, the distance between the emulation header and the processor is greater than six inches. Emula- tion signals TMS, TDI, TDO, and TCK_RET are buffered through the same package.
Page 444 Connections Between the Emulator and the Target System 15.7.2 Using a Target-System Clock Figure 15–4 shows an application with the system test clock generated in the target system. In this application, the TCK signal is left unconnected. Figure 15–4. Target-System-Generated Test Clock Greater Than 6 Inches V CC...
Page 445 Connections Between the Emulator and the Target System 15.7.3 Configuring Multiple Processors Figure 15–5 shows a typical daisy-chained multiprocessor configuration, which meets the minimum requirements of the IEEE 1149.1 specification. The emulation signals in this example are buffered to isolate the processors from the emulator and provide adequate signal drive for the target system.
Page 446 Mechanical Dimensions for the 14-Pin Emulator Connector 15.8 Mechanical Dimensions for the 14-Pin Emulator Connector The JTAG emulator target cable consists of a 3-foot section of jacketed cable, an active cable pod, and a short section of jacketed cable that connects to the target system.
Page 447 Mechanical Dimensions for the 14-Pin Emulator Connector Figure 15–7. 14-Pin Connector Dimensions 0.20 Cable 0.66 Connector, Side View Key, Pin 6 0.100 0.87 Cable 0.100 Connector, Front View Pins 2, 4, 6, 8, 10, 12, 14 Pins 1, 3, 5, 7, 9, 11, 13 Note: All dimensions are in inches and are nominal dimensions, unless otherwise specified.
Page 448 Emulation Design Considerations 15.9 Emulation Design Considerations This section describes the use and application of the scan path linker (SPL), which can simultaneously add all four secondary JTAG scan paths to the main scan path. It also describes the use of the emulation pins and the configuration of multiple processors.
Page 449 Emulation Design Considerations Figure 15–8. Connecting a Secondary JTAG Scan Path to an SPL JTAG 0 DTCK DTDO0 DTMS0 DTDI0 TRST TRST DTDO1 DTMS1 DTDI1 JTAG N DTDO2 DTMS2 DTDI2 TRST DTDO3 DTMS3 DTDI3 The TRST signal from the main scan path drives all devices, even those on the secondary scan paths of the SPL.
Page 450 Emulation Design Considerations 15.9.2 Emulation Timing Calculations for SPL The following examples help you to calculate the emulation timings in the SPL secondary scan path of your system. For actual target timing parameters, see the appropriate device data sheets. Assumptions: Target TMS/TDI setup to TCK high 10 ns su(TTMS)
Page 451 Emulation Design Considerations Of the following two cases, the worst-case path delay is calculated to deter- mine the maximum system test clock frequency. Case 1: Single processor, direct connection, DTMS/DTDO timed from TCK low. d DTMSmax d DTCKHmin su TTMS pd TCK–DTMS TCKfactor [31ns...
Page 452 Emulation Design Considerations 15.9.3 Using Emulation Pins The EMU0/1 pins of TI devices are bidirectional, three-state output pins. When in an inactive state, these pins are at high impedance. When the pins are active, they function in one of the two following output modes: Signal Event The EMU0/1 pins can be configured via software to signal internal events.
Page 453 Emulation Design Considerations Figure 15–9. EMU0/1 Configuration Target Board 1 Pullup Resistor Open Collector EMU0/1 Drivers Backplane Device Device . . . XCNT_ENABLE EMU0/1-IN Pullup Resistor EMU0/1-OUT Target Board m Pullup Resistor To Emulator EMU0 Open Collector EMU0/1 Drivers Device Device .
Page 454 Emulation Design Considerations on the EMU0/1-OUT signal. This pulse must be longer than one TCK period to affect the devices, but less than 10 µs to avoid possible conflicts or retriggering, once the emulation software clears the device’s pins. During a RUNB debugger command or other external analysis count, the EMU0/1 pins on the target device become totem-pole outputs.
Page 455 Emulation Design Considerations Figure 15–10. EMU0/1 Configuration With Additional AND Gate to Meet Timing Requirements Target Board 1 Pullup Resistor Open Collector EMU0/1 Drivers Backplane Device Device . . . XCNT_ENABLE EMU0/1-IN Pullup Resistor EMU0/1-OUT Target Board m Pullup Resistor To Emulator EMU0 Open Circuitry required for >25-ns rising/...
Page 456 Emulation Design Considerations If having devices on one target board stopped by devices on another target board via the EMU0/1 signals is not important, then the circuit in Figure 15–12 can be used. In this configuration, the global-stop capability is lost. It is impor- tant not to overload EMU0/1 with more than 16 devices.
Page 457 For systems that require built-in diagnostics, it is possible to connect the emulation scan path directly to a TI ACT8990 test bus controller (TBC) instead of the emulation header. The TBC is described in the Texas Instruments Ad- vanced Logic and Bus Interface Logic Data Book (literature number SCYD001).
Page 458 Emulation Design Considerations On the TBC, the TMS0 pin drives the TMS pins on each device on the main JTAG scan path. TDO on the TBC connects to TDI on the first device on the main JTAG scan path. TDI0 on the TBC is connected to the TDO signal of the last device on the main JTAG scan path.
Page 459 Index Index 14-pin connector, dimensions 15-13 RAM in cache mode 3-5 14-pin header address modification 6-14 header signals 15-2 address phase (Ta) 8-36 JTAG 15-2 Address pin EA[12] 9-6 2–bit data delay used to discard framing bit, address range 6-9 figure 11-31 address shift 9-32 ’320C6000 devices, features 1-5...
Page 460 1-6, 2-1 timers 12-3 architecture 2-4 TMS320C6201/6202/6701 1-9 bypass 2-4 TMS320C6201/C6701 7-2 fetch packet figure 2-5 TMS320C6201/C6701 program memory flush 2-5 controller 2-2 logical mapping of address 2-5 TMS320C6202 data memory controller 3-7 miss 2-3, 2-5 TMS320C6202 program memory controller 3-3...
Page 461 Index cache RAM 4-3 control register boundary conditions 12-11 control registers 1-9, 4-2, 8-4, 9-5, 9-6, 9-9 chaining EDMA channels by an event 6-34 EDMA 6-6 Channel Chain Enable Register (CCER), control status register 3-4 figure 6-35 figure iii channel chain enable register (CCER) 6-6, 6-34 controller 2-3 Channel Interrupt Enable Register (CIER), data memory 1-6...
Page 462 TMS320C6202 8-4 organization 2-9 expansion bus XCE (0/1/2/3) space control TMS320C6201 revision 2 2-9 register 8-9 TMS320C6201 revision 2, figure 2-10 host port interface block of TMS320C6211 7-5 TMS320C6201 revision 2, table 2-9 internal memory block 4-3 TMS320C6201 revision 3 2-11 L1D, 2–way set associative cache diagram 4-11...
Page 463 EDMA transfer 6-7 access to program memory 2-6 initiating 6-17 DMA controller interconnect to EDMA transfers, synchronization of 6-17 TMS320C6201/C6701 memory mapped EDMA transfers, linking 6-25 modules, figure 5-4 EDMA_TCC10 6-18 DMA global count reload register used as a transfer...
Page 464 Index EMIF to SRAM interface, figure 9-50 event register (ER) 6-6 EMU0/1 Event Set Register (ESR), figure 6-8 configuration 15-19, 15-22 event set register (ESR) 6-6, 6-7 emulation pins 15-18 event set register, ESR 6-17 IN signals 15-18 event–triggered EDMA 6-17 rising edge modification 15-21 events, synchronization 11-7 EMU0/1 signals 15-2, 15-5, 15-6, 15-11, 15-16...
Page 465 Index space control register diagram 8-9 external memory 3-6, 10-2 expansion bus (XB) 1-8 external memory interface 3-7 Expansion Bus Block Diagram, figure 8-2 external memory interface (EMIF) 1-8, 1-9, 2-3, 3-3, 3-7, 4-2, 8-3, 8-4, 9-5, 9-6 Expansion Bus Boot Configuration via Pull Up/Pull 16-bit ROM 9-53 Down Resistors on XD[31:0], figure 8-49...
Page 466 Index clean register 4-22 FIFO Read Mode – Read Timing (glue–less case), clock rate 9-11 figure 8-17 expansion bus arbiter 8-50 FIFO Read Mode – With Glue, figure 8-18 external master to DSP interrupt 8-25 FIFO Write Cycles, figure 8-16 FIFO clock enable (XFCEN) 8-8 first level memory 4-1 FIFO mode 8-50...
Page 467 Index signal descriptions 7-7 software handshaking 7-17 strobes 7-10 general–purpose registers 1-5 write with autoincrement 7-25 general–purpose timers 1-12 write without autoincrement 7-23 generate pulses 12-2 HPI 1-10 global control register 8-8 HPI Block Diagram of TMS320C6211, figure 7-5 global control register diagram 9-9 HPI bootload 3-6 Glue–Less Read FIFO Interface, figure 8-17 HPI control register (HPIC) 7-5...
Page 468 Index internal data RAM address mapping 3-7 interrupt multiplexer high register diagram, figure 13-8 internal master address register 8-6 interrupt multiplexer low register diagram, internal memories 4-2 figure 13-8 internal memory 1-6, 3-6, 4-3 interrupt pending register 6-32 internal memory and cache configurations available interrupt processing 6-6 on the current TMS320C6000 3-2 Interrupt selector 1-8...
Page 469 ’C6202 memory map 10-6 level 1 program cache mode settings 4-6 TMS320C6000, internal configurations 3-2 level–one data cache (L1D) controller 1-7 TMS320C6201 3-2 level–one program cache (L1P) 1-7 TMS320C6202 3-2 line/frame count (FC) 6-12 TMS320C6211 memory map summary 10-7 line/frame index (FIX) 6-12 two–level internal 4-1...
Page 470 Index memory map 2-3 companding data formats 11-51 boot configuration 10-5 companding DLB method 11-52 companding hardware 11-50 memory mapped operation 3-4 companding nonDLB method 11-52 memory mapped registers 9-9 configuration 11-7 memory request priority 9-61 control register 11-7 memory type field (MTYPE) 8-9 CPU interrupts 11-22 memory data delay 11-30...
Page 471 Index XDATDLY 11-30 XSYNCERR 11-47 multichannel buffered serial ports (McBSPs) 1-8 Packing and unpacking 9-14 multiphase frame example 11-32 page boundaries, monitoring 9-25 multiplexed address 8-3 PAL 15-19, 15-20, 15-22 multiplexed device control 9-6 parameter entry of an EDMA event 6-12 multiplier 1-5 Parameter RAM 6-10, 6-11 multivendor interface protocol 1-11...
Page 472 Index program access/cache controller 8-4 Read/Write FIFO Interface With Glue, figure 8-16 program address 4-3 read/write synchronization 6-19 Read/Write Synchronized 2–D Transfer program and data busses 4-1 (No Frame Sync), figure 6-23 program cache control (PCC) 2-3, 4-6 ready signals 8-27 program cache control (PCC) field 4-6 ready status 11-21 program cache mode settings, L1P 4-6...
Page 473 Index EMIF SDRAM timing 9-17 space control 8-9 event 6-6 timer 12-4 event clear 6-6, 6-8 timer counter 12-6 timer period 12-6 event enable 6-6, 6-8 transfer counter 5-16 event processing 6-6 transmit channel enable register (XCER) 11-6 event set 6-6, 6-7, 6-8 transmit control register (XCR) 11-14 expansion bus 8-6 transmit shift register (XSR) 11-4...
Page 474 Index suggested timings 15-21 bus back–off 8-27 byte enable 8-27, 8-41 scan paths, TBC emulation connections for JTAG chip select 8-26, 8-41 scan paths 15-23 clock input 8-26 scratch pad RAM 6-9 control 8-27, 8-41 SCSA standards 1-11 data 8-14 SD_INT 6-18 data bus 8-41 SDA10 pin 9-6...
Page 475 Index SPI Protocol: CLKSTP 11-80 TDM serial port control register (TSPC) TXM bit 11-17, 11-55 SRC Address 6-12 XRDY bit 11-9 SRC address parameter updates 6-30 TDM serial port interface 11-78 SRC/DST Address 6-14 TDO output 15-3 SRC/DST address updates 6-29 TDO signal 15-3, 15-4, 15-6, 15-7, 15-17, 15-23 standard McBSP operation 11-33 test bus controller 15-20, 15-23...
Page 476 3-2 transfer parameters 6-9, 6-13 data memory controller 3-7 transfer with frame synchronization 8-21 internal memory configurations 3-2 read transfer 5-2 TMS320C6201/C6701 block diagram 1-9, 1-10 transfers TMS320C6202 2–dimensional 6-22 cache architecture 3-2 block 5-13 data memory controller 3-7...
Page 477 Index transmit with data overwrite 11-45 word count register 4-8 triggering a power–down 14-4 word index 4-9 write hold 9-12 TRST signal 15-2, 15-5, 15-6, 15-11, 15-16, 15-24 write hold and read hold bit fields 9-13 TSTAT parameters 12-10 write hold fields 9-14 two level memory architecture 4-1 write interface 8-15 two–dimensional (2D) transfers 6-20...

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