Mcbsp Receive/Transmit Element Length Configuration - Texas Instruments TMS320C6201 Reference Manual

Data Transmission and Reception
11.3.4.5 Element Length: (R/X)WDLEN(1/2)
Table 11–11. McBSP Receive/Transmit Element Length Configuration
11.3.4.6 Data Packing using Frame Length and Element Length
11-28
The (R/X)WDLEN(1/2) fields in the receive/transmit control register determine
the element length in bits per element for the receiver and the transmitter for
each phase of the frame, as indicated in Table 11–9. Table 11–11 shows how
the value of these fields selects particular element lengths in bits. For the exam-
ple in Figure 11–8, (R/X)WDLEN1 = 001b and (R/X)WDLEN2 = 000b. If
(R/X)PHASE = 0, indicating a single-phase frame, (R/X)WDLEN2 is not used
by the McBSP and its value does not matter.
(R/X)WDLEN
The frame length and element length can be manipulated to effectively pack
data. For example, consider a situation in which four 8-bit elements are trans-
ferred in a single-phase frame, as shown in Figure 11–10. In this case:
(R/X)PHASE = 0, indicating a single-phase frame
(R/X)FRLEN1 = 0000011b, indicating a 4-element frame
(R/X)WDLEN1 = 000b, indicating 8-bit elements
In this situation, four 8-bit data elements are transferred to and from the McBSP
by the CPU or the DMA controller. Four reads of DRR and four writes of DXR
are necessary for each frame.
McBSP
Element
Length (Bits)
(1/2)
000 8
001 12
010 16
011 20
100 24
101 32
110 Reserved
111 Reserved