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Figure 4–19. L2 Flush Word Count Register Fields (L2FWC)
31
Figure 4–20. L2 Clean Base Address Register Fields (L2CBAR)
31
Figure 4–21. L2 Clean Word Count Register Fields (L2CWC)
31
rsvd
R,+x
To clean a range of address from the L2, write the word-aligned address for
the start of the clean into the L2CBAR. The number of words to clean is equal
to the value written into the L2CWC register. The L2 controller then searches
all L2 cache blocks for all lines whose external memory address falls within the
range from L2CBAR to L2CBAR+L2CWC–4 and copies that data through the
EDMA to external memory space. The L1D is snooped to ensure that the
correct data is stored in the original memory location. In addition to snooping
data from the L1D, any L1P or L1D lines that cache a cleaned address are
invalidated. The L2 clean occurs in the background and does not stall any
pending CPU accesses. The clean begins when the L2CWC is written,
therefore you should take care to ensure that the L2CBAR register is set up
correctly prior to writing the L2CWC. If L2CBAR or L2CWC are not aligned to
the L2 line size (32 words), all lines which contain the words specified are inval-
idated. However only those words that are contained in the range from
L2CBAR to L2CBAR + L2CWC–4 are saved to the external memory space.
Figure 4–20 shows the fields in the L2CBAR register. Figure 4–21 shows the
fields in the L2CWC register.
L2 Clean Base Address
rsvd
R,+x
If more than one block invalidation, block flush, or block clean is requested at
one time, the CPU is stalled until all are completed. For example, if an L1P
invalidate is being processed and you set up an L2 clean by writing to the
L2CWC register, the CPU is stalled until both the L1P invalidate and L2 clean
are complete.
TMS320C6211/C6711 Two-Level Internal Memory
16
15
RW,+x
16
15
L2 Description
L2 Flush Word Count
R,+x
L2 Clean Word Count
R,+x
0
0
0
4-23
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