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Expansion Bus I/O Port Operation
8.4 Expansion Bus I/O Port Operation
8-10
For external IO port accesses on the expansion bus, the XBE signals act as
address signals XA[5:2]. You can use the address signals to address as many
as 16 different R/W peripherals or 32 FIFOs in each XCE space. For the FIFO
interface, 32 devices are possible since a separate Read and Write FIFO can
be located at each address.
Access to the expansion bus I/O port can only be done through the DMA
channels 0 through 3. The DMEMC does not have direct access to the
expansion bus. Therefore, load and store (LD/ST) commands to the memory
spaces of the expansion bus I/O port via the CPU are not allowed, and result
in undefined operation. A DMA transfer cannot occur from one XCE space to
another XCE space. Also, a host port transaction cannot access any of the
XCE spaces.
For reads, care must be taken to ensure that contention on the data bus does
not occur when switching from one peripheral to the next in the same XCE
space. The DMA can accomplish this since inactive cycles occur when the
DMA switches from one frame to the next. The DMA can be set up to read (or
write) a frame from each of the peripherals or FIFOs in turn. For example, the
element index can be set to 0 and the frame index can be set to a multiple of
4 (ensure word strides), thus incrementing to a different location after each
frame has completed.
Although the expansion bus does not explicitly support memory widths of less
than 32 bits, the DMA can be used to read/write to 8-bit or 16-bit peripherals
or FIFOs by controlling the byte/half-word logical addressing. For example, if
an 8-bit-wide FIFO is in XCE2, then the DMA ESIZE bit-field can specify 8-bit
transfers. The lower two address bits in the DMA source or destination address
register determines the byte lane used for accessing the I/O port. If the bottom
two bits are 00b (word aligned), then only XD[7:0] is used for valid data. If
A[1:0] = 01b, then XD[15:8] is used (see Figure 8–5 and Table 8–6).
Alternatively, if 16-bit (or 8-bit) peripherals are used, the DMA element index
can be set up such that the stride value causes a read from alternating byte
lanes during each read transfer. For example, the first access can be to ad-
dress A[5:0] = xxxx00b, causing the lower half of the data bus to be driven by
the peripheral. If the next address is A[5:0] = xxxx10b, the top half of the data
bus is driven by the other peripheral (or FIFO) and no bus contention occurs.
The only address signals which are externally provided are A[5:2]. If address
decoding is required to address a specific peripheral or FIFO, these should be
modified as necessary by the DMA to ensure that peripherals are only ad-
dressed when appropriate (see Figure 8–6 and Table 8–7).
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