Sdram Refresh - Texas Instruments TMS320C6201 Reference Manual

SDRAM Interface
9.4.3

SDRAM Refresh

9-26
For the 'C6211/C6711, up to four pages of SDRAM can be opened simulta-
neously. These pages can be within a single CE space, or spread over all CE
spaces. For example, two pages can be open in CE0 and CE2, or four pages
can be open in CE0. The combination of SDCSZ, SDRSZ, and SDBSZ control
which logical address bits are compared to determine if a page is open. For
example, a typical 2-bank
banks,eleven row address bits, and eight column address bits. A 32-bit-wide
SDRAM uses logical address bits A[9:2] (two-bit offset for word addressing)
to specify the column being accessed. Bits A[20:10] specify the row offset, and
bit A[21] specifies the bank. Logical address bites A[31:28] determines the CE
space used. If a page boundary is crossed during an access to the same CE
space, the 'C6211/C6711 performs a DEAC command and starts a new row
access.
Simply ending the current access is not a condition that forces the active
SDRAM row to be closed. The EMIF leaves the active row open until it becomes
necessary to close it. This feature decreases the deactivate-reactivate over-
head and allows the interface to capitalize fully on address locality of memory
accesses.
The RFEN bit in the SDRAM control register selects the SDRAM refresh mode
of the EMIF. A value of 0 in RFEN disables all EMIF refreshes, and you must
ensure that refreshes are implemented in an external device. A value of 1 in
RFEN enables the EMIF to perform refreshes of SDRAM.
Refresh commands (REFR) enable all CE signals for all CE spaces selected to
use SDRAM (with the MTYPE field of the CE space control register). REFR is
automatically preceded by a DCAB command. This ensures that all CE spaces
selected with SDRAM are deactivated. Following the DCAB command, the EMIF
begins performing trickle refreshes at a rate defined by the period value in the
EMIF SDRAM control register, provided no other SDRAM access is pending.
For the 'C6201/C6202/C6701, the SDRAM interface monitors the number of re-
fresh requests posted to it and performs the refreshes. Within the EMIF SDRAM
control block, a 2-bit counter monitors the backlog of refresh requests. The
counter increments once for each refresh request and decrements once for
each refresh cycle performed. The counter saturates at the values of 11 and 00.
At reset, the counter is automatically set to 11 to ensure that several refreshes
occur before accesses begin.
512K 16-bit SDRAM has settings of two