Priority Queue Status Register(Pqsr) - Texas Instruments TMS320C6201 Reference Manual

Figure 6–17. Priority Queue Status Register(PQSR)
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6.15 EDMA Performance
Resource Arbitration and Priority Processing / EDMA Performance
The priority queue status register (PQSR) shown in Figure 6–17 indicates if
the transfer request queue is empty on the three priority levels ( 0 – urgent,
1 – high, and 2 – low). EDMA transfers can be submitted only with priority level
one or two. The urgent priority level '0' is reserved for L2 requests. Status bits
PQ[2:0] in the PQSR provide the status of the three queues. The three LSBs
in this register, PQ[2:0], if set to '1' indicate that there are no requests pending
in the respective priority level. If PQSR[0] is '1', this means all L2 requests for
data movement have been completed and there are no requests pending.
rsvd
R, +0
The three priority queue bits are mainly used for emulation, context switching
for multitasking applications, and submitting requests with a higher priority –
when possible. For the emulation case, the PQ0 bit is used to ensure that all
cache requests via L2 are completed before updating any memory windows
for the emulation halt. Another use is to determine the right time to do a task
switch. For example, allocating L2 SRAM to a new task after ensuring that
there are no EDMA transfer requests in progress which might write to L2
SRAM. Lastly, the PQ bits in PQSR can be used to allocate or submit requests
judiciously on the lower two priority levels (by the EDMA or HPI) depending on
which priority queue is empty. Therefore a low-priority request can be up-
graded to a high priority if required. This helps prevent all requests from being
queued under the same priority level which could lead to EDMA stalls.
The EDMA can perform element transfers with single cycle throughput
provided the source and destination are two different resources that provide
a single-cycle throughput. The performance can be limited by:
EDMA stalls: When there are multiple transfer requests on the same prior-
ity level
EDMA accesses to L2 SRAM with lower priority than CPU
3 2
PQ2
R, +1
EDMA Controller
EDMA Performance
1 0
PQ1 PQ0
R, +1 R, +1
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