Synch Fifo Pin Description - Texas Instruments TMS320C6201 Reference Manual

Expansion Bus I/O Port Operation
Table 8–8. Synch FIFO Pin Description
Signal Signal
(I/O/Z) Signal Purpose
Name
XFCLK O FIFO clock output
XD[31:0] I/O/Z Data
XCEx O FIFO read
enable/write
enable/chip Select
XWE O FIFO write enable
XRE O FIFO read enable
XOE O FIFO output
enable
XBE[3:0]/ O/Z Expansion bus
XA[5:2] address
8-14
R/W Mode
Programmable to either 1/2, 1/4, 1/6, or 1/8 of the CPU clock
frequency. If CPU clock = 250 MHz, then XFCLK = 125, 62.5, 41.7 or
31.25 MHz. The XFCLK continues to clock even when the DSP
releases ownership of the XBUS.
Data lines
Active for both read and write
transactions. They should
logically OR-ed with output control
signals externally to
dedicated controls for a FIFO. Also
can be used directly as FIFO write
enable signal for a single write FIFO
per XCE space.
Write-enable signal for FIFO. Must
be logically OR-ed
corresponding XCE
ensure that only one FIFO is
addressed at a time.
Read-enable signal for FIFO. Must
be logically OR-ed
corresponding XCE
ensure that only one FIFO is
addressed at a time.
Shared output enable signal. Must
be logically OR-ed
corresponding XCE
ensure that only one FIFO is
addressed at a time.
Operate as XA[5:2]. Can be de-
coded to specify up to 16 different
addresses, enabling interface with
glue to 16 Read FIFOs and 16 Write
FIFOs in a single XCE space.
Signal Function
Read Mode
Acts as read enable
be signal(XCE3 only)
create
with
signal to
with
signal to
Dedicated output enable signal
with in XCE3 if FIFO read mode is
signal to selected. If selected, this signal
is disabled for all other modes .