Timing Requirements; Tms320C6201/C6202/C6701 Sdram Timing Parameters - Texas Instruments TMS320C6201 Reference Manual

SDRAM Interface
9.4.6

Timing Requirements

Table 9–15. TMS320C6201/C6202/C6701 SDRAM Timing Parameters
Parameter Description
t REFR command to ACTV, MRS, or subsequent REFR command
RC
t ACTV command to READ or WRT command
RCD
t DCAB command to ACTV, MRS, or REFR command
RP
t ACTV command to DEAC to DCAB command
RAS
t Overlap between read data and a DCAB command
nEP
† CLKOUT2 cycles apply to the 'C6201/C6202/C6701, and ECLKOUT cycles apply to the 'C6211/C6711.
9-34
Table 9–15 shows five SDRAM timing parameters that decouple the EMIF from
SDRAM speed limitations. Three of these parameters are programmable via
the EMIF SDRAM control register; the remaining two are assumed to be static
values. The three programmable values ensure that EMIF control of SDRAM
obeys these minimum timing requirements. Consult the SDRAM data sheet
for information on the parameters that are appropriate for your particular
SDRAM.
Value in CLKOUT2/
ECLKIN2 Cycles
TRC + 1
TRCD + 1
TRP +1
7
2