Internal Program Memory Mode Summary - Texas Instruments TMS320C6201 Reference Manual

Internal Program Memory
Table 2–1. Internal Program Memory Mode Summary
2.2.2 Cache Architecture
2-4
Cache freeze ensures that critical program data is not overwritten in the
cache.
Cache bypass: When the cache is bypassed, any program read fetches
data from external memory. The data is not stored in the cache memory.
As in cache freeze, the cache retains its state in cache bypass. This mode
ensures that external program data is being fetched.
Internal Program
Memory Mode
Mapped
Cache enabled
Cache freeze
Cache bypass
Note:
If you change the operation mode of the PMEMC, you should use the follow-
ing assembly routine to ensure correct operation of the PMEMC. This routine
enables the cache. To change the PMEMC operation mode to a state other
than cache enable, you should modify line four of the routine to correspond
the the value of PCC that you want moved into B5. For example, to put the
cache into mapped mode 0000h should be moved into B5. The CPU regis-
ters used in this example have no significance. Any of the registers A0–A15
or B0–B15 can be used in the program.
.align 32
MVC .S2 CSR,B5
|| MVK .S1 0xff1f,A5
AND .L1x A5,B5,A5
|| MVK S2 0x0040,B5 ;set cache enable mask
OR .L2x A5,B5,B5
MVC .S2 B5,CSR
NOP 4
NOP
The architecture of the cache is directly mapped. The 64K byte cache contains
2K fetch packets, thus, 2K frames. The width of the cache (the frame size) is
256 bits. Each frame in the cache is one fetch packet.
PCC
Description
Value
000 Cache disabled (default state at reset)
010 Cache accessed and updated on reads
011 Cache accessed but not updated on reads
100 Cache not accessed or updated on reads
Other Reserved
;copy control status register
;clear PCC field of CSR value
;set cache enable bit
;update CSR to enable cache