Tms320C6201/C6701/C6202 Internal Memory Configurations; Tms320C6201/C6701/C6202 Cache Architectures - Texas Instruments TMS320C6201 Reference Manual

TMS320C6202 Program Memory Controller
3.1 TMS320C6202 Program Memory Controller
Table 3–1. TMS320C6201/C6701/C6202 Internal Memory Configurations
Device CPU
'C6201 6200
'C6701 6700
'C6202 6200
Table 3–2. TMS320C6201/C6701/C6202 Cache Architectures
3-2
The TMS320C6202 program memory controller (PMEMC) provides all of the
functionality available in the TMS320C6201 revision 3. The PMEMC operates
as either a 128K byte memory or direct-mapped cache. In addition to the
memory/cache, the C6202 provides 128K bytes of memory that operates as
a memory-mapped block. To achieve this functionality, the block of program
memory has been expanded to 128K bytes. A second 128K byte block of pro-
gram memory has been added. These two blocks can be accessed indepen-
dently, allowing for program fetch from one block by the CPU to occur in paral-
lel and without interfering with a DMA transfer with the other block of program
memory. Table 3–1 and Table 3–2 compare the internal memory and cache
configurations available on the current TMS320C6000 devices. Figure 3–1
shows a block diagram of the connections between the C6202 CPU, PMEMC,
and memory blocks. The addresses shown in Figure 3–1 are for operation in
memory map mode 1.
Internal
Memory
Total Memory
Architecture
(Bytes)
Harvard 128K
Harvard 128K
Harvard 384K
Cache Space
'C6201 program
'C6701 program
'C6202 program
Program Memory
(Bytes)
64K (map/cache)
64K (map/cache)
128K (map)
128K (map/cache)
Size (Bytes) Associativity
64K Direct mapped
64K Direct mapped
128K Direct mapped
Data Memory
(Bytes)
64K (map)
64K (map)
128K (map)
Line Size (Bytes)
32
32
32