Texas Instruments TMS320C6711D User Manual
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Texas Instruments TMS320C6711D User Manual

Texas Instruments TMS320C6711D User Manual

Floating point digital signal processor
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D
Excellent-Price/Performance Floating-Point
Digital Signal Processor (DSP):
TMS320C6711D
− Eight 32-Bit Instructions/Cycle
− 167-, 200-, 250-MHz Clock Rates
− 6-, 5-, 4-ns Instruction Cycle Time
− 1000, 1200, 1500 MFLOPS
D
Advanced Very Long Instruction Word
(VLIW) C67x DSP Core
− Eight Highly Independent Functional
Units:
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
D
Instruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
− Normalization
D
L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
RAM/Cache
(Flexible Data/Program Allocation)
D
Device Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
D
Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
† IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡ These values are compatible with existing 1.26V designs.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FLOATING POINT DIGITAL SIGNAL PROCESSOR
D
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POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005
32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
16-Bit Host-Port Interface (HPI)
Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
Two 32-Bit General-Purpose Timers
Flexible Software Configurable PLL-Based
Clock Generator Module
A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins
†
IEEE-1149.1 (JTAG
)
Boundary-Scan-Compatible
272-Pin Ball Grid Array (BGA) Package
(GDP and ZDP Suffixes)
CMOS Technology
− 0.13-µm/6-Level Copper Metal Process
3.3-V I/O, 1.4-V Internal (−250)
3.3-V I/O, 1.20-V Internal
Copyright  2005, Texas Instruments Incorporated
TMS320C6711D
‡
1

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  • Page 1 Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C67x and C67x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. † IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

  • Page 2: Table Of Contents

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 revision history ........

  • Page 3: Revision History

    The TMS320C6711D device-specific documentation has been split from TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D Floating−Point Digital Signal Processors, literature number SPRS088N, into a separate Data Sheet, literature number SPRS292. It also highlights technical changes made to SPRS292 to gen- erate SPRS292A; these changes are marked by “[Revision A]” in the Revision History table below.

  • Page 4: Gdp And Zdp Bga Packages (Bottom View)

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 GDP and ZDP BGA packages (bottom view) GDP and ZDP 272-PIN BALL GRID ARRAY (BGA) PACKAGES † † The ZDP mechanical package designator represents the version of the GDP package with lead−free balls. For more detailed information, see the Mechanical Data section of this document.

  • Page 5: Description

    TMS320C6000 is a trademark of Texas Instruments. Windows is a registered trademark of the Microsoft Corporation. † Throughout the remainder of this document, the TMS320C6711D shall be referred to as its individual full device part number or abbreviated as C6711D or 11D.

  • Page 6: Device Characteristics

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 device characteristics Table 1 provides an overview of the C6711D DSP. The table shows significant features of the device, including the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more details on the C6000...

  • Page 7: Device Compatibility

    TMS320C6711 DSP application reports (literature number SPRA474 and SPRA522, respectively). † This value is compatible with existing 1.26V designs. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D †...

  • Page 8: Functional Block And Cpu (Dsp Core) Diagram

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 functional block and CPU (DSP core) diagram SDRAM External SBSRAM Memory Interface SRAM (EMIF) ROM/FLASH Timer 0 I/O Devices Timer 1 Multichannel Buffered Serial Port 1...

  • Page 9: Cpu (Dsp Core) Description

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute.
  • Page 10 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU (DSP core) description (continued) LD1 32 MSB Data Path A LD1 32 LSB LD2 32 LSB Data Path B LD2 32 MSB † In addition to fixed-point instructions, these functional units execute floating-point instructions.

  • Page 11: Memory Map Summary

    0 and can be used as both program and data memory. The configuration registers for the common peripherals are located at the same hex address ranges. The external memory address ranges in the device begin at the address location 0x8000 0000. Table 2. TMS320C6711D Memory Map Summary MEMORY BLOCK DESCRIPTION Internal RAM (L2)

  • Page 12: Peripheral Register Descriptions

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions Table 3 through Table 14 identify the peripheral registers for the device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).
  • Page 13 Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event Reload/link parameters for Event 0−15 Reload/link parameters for Event 0−15 Reload/link parameters for Event 0−15 Scratch pad area (2 words) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D COMMENTS...
  • Page 14 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 2. Word 0 EDMA Channel Options Parameter (OPT)
  • Page 15 GPIO interrupt polarity register Reserved Table 12. HPI Registers REGISTER NAME HPI data register Host read/write access only HPI address register Host read/write access only HPI control register Both Host/CPU read/write access Reserved • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D COMMENTS...
  • Page 16 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 peripheral register descriptions (continued) Table 13. Timer 0 and Timer 1 Registers HEX ADDRESS RANGE TIMER 0 TIMER 1 0194 0000 0198 0000 0194 0004 0198 0004...

  • Page 17: Signal Groups Description

    IEEE Standard 1149.1 Reserved (JTAG) Emulation Control/Status (Host-Port Interface) Data Register Select Control Half-Word Select • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D RESET EXT_INT7 ‡ EXT_INT6 ‡ EXT_INT5 ‡ EXT_INT4 ‡ • • • HR/W HDS1 HDS2 HRDY HINT...
  • Page 18 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) ED[31:0] EA[21:2] TOUT1 TINP1 CLKX1 FSX1 CLKR1 FSR1 DR1 † CLKS1 † † For proper device operation, these pins must be externally pulled up with a 10-kΩ resistor.
  • Page 19 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 signal groups description (continued) GP[7](EXT_INT7) GP[6](EXT_INT6) GP[5](EXT_INT5) GP[4](EXT_INT4) GPIO CLKOUT2/GP[2] General-Purpose Input/Output (GPIO) Port Figure 4. Peripheral Signals (Continued) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443...

  • Page 20: Device Configurations

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 On this device, bootmode and certain device configurations/peripheral selections are determined at device reset. Also, other device configurations (e.g., EMIF input clock source) are software-configurable via the device configurations register (DEVCFG) [address location 0x019C0200] after device reset.

  • Page 21: Configuration Pin

    10 − CE1 width 16-bit, Asynchronous external ROM boot with default timings 11 − CE1 width 32-bit, Asynchronous external ROM boot with default timings 0 – Reserved. Do not use. 1 − CLKIN square wave [default] • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D †...
  • Page 22 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 DEVICE CONFIGURATIONS (CONTINUED) DEVCFG register description The device configuration register (DEVCFG) allows the user control of the EMIF input clock source for the device. For more detailed information on the DEVCFG register control bits, see Table 16 and Table 17.

  • Page 23: Terminal Functions

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 TERMINAL FUNCTIONS The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors and a functional pin description.
  • Page 24 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † IPU ‡ ‡ NAME GDP/ CLKIN CLKOUT2 (/GP0[2]) CLKOUT3 CLKMODE0 PLLHV TRST § EMU5 I/O/Z EMU4 I/O/Z EMU3 I/O/Z †...

  • Page 25: Resets And Interrupts

    • Edge-driven Edge-driven • Polarity independently selected via the External Interrupt Polarity Register • Polarity independently selected via the External Interrupt Polarity Register bits (EXTPOL.[3:0]), in addition to the GPIO registers. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...
  • Page 26 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † IPU ‡ ‡ NAME GDP/ HINT HCNTL1 HCNTL0 HHWIL HR/W HD15 HD14 § HD13 § HD12 § HD11 HD10 HD8 §...
  • Page 27 – ECLKOUT enabled to clock (default) Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM address strobe Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM output enable Asynchronous memory write enable/SDRAM write enable/SBSRAM write enable Asynchronous memory ready input • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...
  • Page 28 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † IPU ‡ ‡ NAME GDP/ EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12 EA11 EA10 ED31...
  • Page 29 Because it is common for some ICs to 3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even when an external device is driving the pin. Receive clock Transmit clock • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...
  • Page 30 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL IPD/ IPD/ TYPE † TYPE † IPU ‡ NAME GDP/ MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1) (CONTINUED) FSR1 I/O/Z FSX1 I/O/Z MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
  • Page 31 (core power). For old designs, this can be left unconnected. Reserved [For new designs, it is recommended that this pin be connected directly to V ss (ground). For old designs, this pin can be left unconnected. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...
  • Page 32 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL TYPE † TYPE † NAME GDP/ 3.3-V supply voltage 3.3-V supply voltage DV DD DV DD (see the power-supply decoupling portion of this data sheet) (see the power-supply decoupling portion of this data sheet) 1.4-V supply voltage (-250)

  • Page 33: Ground Pins

    † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter) FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) DESCRIPTION DESCRIPTION SUPPLY VOLTAGE PINS (CONTINUED) GROUND PINS • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...
  • Page 34 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SIGNAL SIGNAL TYPE † TYPE † NAME GDP/ Ground pins # Ground pins # The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground and act as...
  • Page 35 † I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter) FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 Terminal Functions (Continued) DESCRIPTION DESCRIPTION GROUND PINS (CONTINUED) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...

  • Page 36: Development Support

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 development support TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

  • Page 37: Device Support

    The ZDP package, like the GDP package, is a 272-ball plastic BGA only with Pb-free balls. For device part numbers and further ordering information for TMS320C6711D in the GDP and ZDP package types, see the TI website (http://www.ti.com) or contact your TI sales representative.
  • Page 38 § For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this document or the TI website (www.ti.com). Figure 5. TMS320C6711D DSP Device Nomenclature MicroStar BGA and PowerPAD are trademarks of Texas Instruments. C 6711D GDP TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
  • Page 39 TMS320C6711, TMS320C6711B, TMS320C6711C, and TMS320C6711D DSP devices. The TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number SPRA889A or later) discusses the power consumption for user applications with the TMS320C6713B, TMS320C6712D, and TMS320C6711D DSP devices.

  • Page 40: Cpu Csr Register Description

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 CPU CSR register description The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1).
  • Page 41 = PD1, wake-up by an enabled or not enabled interrupt = PD2, wake-up by a device reset = PD3, wake-up by a device reset = Reserved Cache Enabled / Cache accessed and updated on reads. Cache Enabled / 2-Way Cache • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...

  • Page 42: Cache Configuration (Ccfg) Register Description

    EDMA will assume a higher priority than the L1D memory system when accessing L2 memory. For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory accesses blocked, see the TMS320C6711/TMS320C6711B/TMS320C6711C/TMS320C6711D Digital Signal Processors Silicon Errata (literature number SPRZ173K or later).

  • Page 43: Interrupt Sources And Interrupt Selector

    01100 00000 DSPINT 01101 00001 TINT0 01110 00010 TINT1 01111 10000 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D Table 21. Interrupt Selector INTERRUPT MODULE EVENT DSPINT TINT0 Timer 0 TINT1 Timer 1 SDINT EMIF GPINT4 † GPIO GPINT5 †...

  • Page 44: Edma Module And Edma Selector

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 EDMA module and EDMA selector The C67x EDMA for the device also supports up to 16 EDMA channels. Four of the sixteen channels (channels 8−11) are reserved for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices. On the device, the user, through the EDMA selector registers, can control the EDMA channels servicing peripheral devices.
  • Page 45 R−0 Reserved R−0 24 23 22 21 Reserved R−0 Reserved R−0 DESCRIPTION • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D 20 19 EVTSEL2 R/W−00 0010b EVTSEL0 R/W−00 0000b 20 19 EVTSEL6 R/W−00 0110b EVTSEL4 R/W−00 0100b 20 19 EVTSEL14 R/W−00 1110b...

  • Page 46: Pll And Pll Controller

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller The device includes a PLL and a flexible PLL controller peripheral consisting of a prescaler (D0) and four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other peripherals).
  • Page 47 CK2EN = 1 (EMIF GBLCTL.[3]) OD1EN = 1 (OSCDIV1.[15]) EKSRC = 0 (DEVCFG.[4]) EKEN = 1 (EMIF GBLCTL.[5]) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D UNIT µs DESCRIPTION SYSCLK2 selected [default] Derived from CLKIN SYSCLK3 selected [default]. To select ECLKIN as source: EKSRC = 1 (DEVCFG.[4]) and...

  • Page 48: Clock Signal

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) Table 28. PLL Clock Frequency Ranges CLOCK SIGNAL CLOCK SIGNAL PLLREF (PLLEN = 1) PLLOUT SYSCLK1 SYSCLK3 (EKSRC = 0) † SYSCLK2 rate must be exactly half of SYSCLK1.
  • Page 49 Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down directly from input reference clock. Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down from PLL output. • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D Reserved PLLPWRDN PLLEN R/W−0 R/W−0b RW−0...
  • Page 50 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) PLLM Register (0x01B7 C110) 28 27 12 11 Reserved R−0 Legend: R = Read only, R/W = Read/Write; -n = value after reset Table 30.
  • Page 51 10010 = 10011 = 10100 = 10101 = 10110 = 10111 = 11000 = 11001 = 11010 = 11011 = 11100 = 11101 = 11110 11111 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D 20 19 PLLDIVx R/W−x xxxx †...
  • Page 52 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 PLL and PLL controller (continued) OSCDIV1 Register (0x01B7 C124) 28 27 12 11 OD1EN Reserved R/W−1 Legend: R = Read only, R/W = Read/Write; -n = value after reset The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3.

  • Page 53: General-Purpose Input/Output (Gpio)

    SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 24 23 Reserved R/W-1 R/W-1 R/W-1 24 23 Reserved R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D — — — R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 R/W-0...

  • Page 54: Power-Down Mode Logic

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 power-down mode logic Figure 11 shows the power-down mode logic on the device. Clock CLKIN † External input clocks, with the exception of CLKOUT3 and CLKIN, are not gated by the power-down mode logic.
  • Page 55 PD2 and PD3 modes can only be aborted by device reset. Table 33 summarizes all the power-down modes. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 R/W-0 R/W-0 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D R/W-0...

  • Page 56: Power Down Mode

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 Table 33. Characteristics of the Power-Down Modes PRWD FIELD POWER-DOWN (BITS 15−10) MODE 000000 No power-down 001001 Wake by an enabled interrupt Wake by an enabled or...

  • Page 57: Power-Supply Decoupling

    FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 DV DD Schottky Diode C6000 CV DD V SS Figure 13. Schottky Diode Diagram • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...

  • Page 58: Ieee 1149.1 Jtag Compatibility Statement

    DSP or exercise the DSP’s boundary scan functionality. The TMS320C6711D DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this pin is not routed out.

  • Page 59: Emif Device Speed

    143 MHz 32-bit SDRAM (−7) 166 MHz 32-bit SDRAM (−6) 183 MHz 32-bit SDRAM (−55) 200 MHz 32-bit SDRAM (−5) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D MAXIMUM ACHIEVABLE MAXIMUM ACHIEVABLE EMIF-SDRAM INTERFACE SPEED 100 MHz For short traces, SDRAM data...

  • Page 60: Emif Big Endian Mode Correctness

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 EMIF big endian mode correctness The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For the device, Little Endian is the default setting.

  • Page 61: Bootmode

    Prior to deasserting RESET (low−to−high transition), the core and I/O voltages should be at their proper operating conditions and CLKIN should also be running at the correct frequency. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...

  • Page 62: Absolute Maximum Ratings Over Operating Case Temperature Range

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 absolute maximum ratings over operating case temperature range (unless otherwise noted) Supply voltage range, CV (see Note 2) Supply voltage range, DV (see Note 2) Input voltage range .

  • Page 63: Supply Voltage And Operating Case Temperature

    McBSP: 2 channels at E1 rate Timers: 2 timers at maximum rate The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D/12D/13B Power Consumption Summary application report (literature number SPRA889A). FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A −...

  • Page 64: Parameter Measurement Information

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION 42 Ω 3.5 nH 4.0 pF 1.85 pF NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account.
  • Page 65 FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 Minimum Risetime V IH (min) Waveform Valid Region t = 0.3 t c (max) † • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D V OS (max) V IL (max) Ground...

  • Page 66: Timing Parameters And Board Routing Analysis

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameters and board routing analysis The timing parameter values specified in this data sheet do not include delays by board routings. As a good board design practice, such delays must always be taken into account.
  • Page 67 Minimum DSP setup time External device hold time requirement External device setup time requirement Control signal route delay External device hold time External device access time DSP hold time requirement DSP setup time requirement Data route delay • HOUSTON, TEXAS 77251−1443 TMS320C6711D...

  • Page 68: Input And Output Clocks

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 †‡§ timing requirements for CLKIN t c(CLKIN) Cycle time, CLKIN t w(CLKINH) Pulse duration, CLKIN high t w(CLKINL) Pulse duration, CLKIN low t t(CLKIN) Transition time, CLKIN †...
  • Page 69 FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 PARAMETER Figure 23. CLKOUT2 Timings PARAMETER Figure 24. CLKOUT3 Timings • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D †‡ GDPA-167 ZDPA−167 −200 UNIT −250 C2 − 0.8 C2 + 0.8 (C2/2) −...
  • Page 70 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 INPUT AND OUTPUT CLOCKS (CONTINUED) timing requirements for ECLKIN t c(EKI) Cycle time, ECLKIN t w(EKIH) Pulse duration, ECLKIN high t w(EKIL) Pulse duration, ECLKIN low...

  • Page 71: Asynchronous Memory Timing

    § Select signals include: CEx, BE[3:0], EA[21:2], and AOE. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 †‡§ (see Figure 27−Figure 28) PARAMETER • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D GDPA-167 ZDPA−167 −200 UNIT −250 GDPA-167 ZDPA−167 −200 UNIT −250...
  • Page 72 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 ASYNCHRONOUS MEMORY TIMING (CONTINUED) Setup = 2 ECLKOUT BE[3:0] EA[21:2] ED[31:0] AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † ARDY † AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE, respectively, during asynchronous memory accesses.
  • Page 73 Figure 28. Asynchronous Memory Write Timing FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 Strobe = 3 Not Ready Address Write Data • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D Hold = 2...

  • Page 74: Synchronous-Burst Memory Timing

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS-BURST MEMORY TIMING timing requirements for synchronous-burst SRAM cycles t su(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high t h(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high †...
  • Page 75 † ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM accesses. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 Figure 29. SBSRAM Read Timing Figure 30. SBSRAM Write Timing • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...

  • Page 76: Synchronous Dram Timing

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 timing requirements for synchronous DRAM cycles t su(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high t h(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high †...
  • Page 77 † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. Figure 31. SDRAM Read Command (CAS Latency 3) FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...
  • Page 78 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUT BE[3:0] EA[21:13] EA[11:2] EA12 ED[31:0] AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
  • Page 79 FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 ACTV Bank Activate Row Address Row Address Figure 33. SDRAM ACTV Command DCAB Figure 34. SDRAM DCAB Command • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...
  • Page 80 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 SYNCHRONOUS DRAM TIMING (CONTINUED) ECLKOUT BE[3:0] EA[21:13] EA[11:2] EA12 ED[31:0] AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses.
  • Page 81 † ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM accesses. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 MRS value Figure 37. SDRAM MRS Command • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D...

  • Page 82: Hold/Holda Timing

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 timing requirements for the HOLD/HOLDA cycles t h(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low † E = ECLKIN period in ns switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles...

  • Page 83: Busreq Timing

    Delay time, ECLKOUT high to BUSREQ valid ECLKOUT BUSREQ FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 BUSREQ TIMING PARAMETER Figure 39. BUSREQ Timing • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D GDPA-167 ZDPA−167 −200 UNIT −250...

  • Page 84: Reset Timing

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 †‡ timing requirements for reset t w(RST) Pulse duration, RESET Setup time, HD boot configuration bits valid before RESET high § t su(HD) Hold time, HD boot configuration bits valid after RESET high §...
  • Page 85 (when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8. FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 RESET TIMING (CONTINUED) Phase 2 Figure 40. Reset Timing • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D Phase 3...

  • Page 86: External Interrupt Timing

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005 timing requirements for external interrupts Width of the NMI interrupt pulse low t w(ILOW) t w(ILOW) Width of the EXT_INT interrupt pulse low Width of the NMI interrupt pulse high...

  • Page 87: Host-Port Interface Timing

    § Select signals include: HCNTL[1:0], HR/W, and HHWIL. FLOATING POINT DIGITAL SIGNAL PROCESSOR HOST-PORT INTERFACE TIMING †‡ (see Figure 42, Figure 43, Figure 44, and • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 GDPA−167 ZDPA−167 −200 UNIT −250...
  • Page 88 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 HOST-PORT INTERFACE TIMING (CONTINUED) switching characteristics over recommended operating conditions during host-port interface †‡ cycles (see Figure 42, Figure 43, Figure 44, and Figure 45) Delay time, HCS to HRDY §...
  • Page 89 ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 43. HPI Read Timing (HAS Used) FLOATING POINT DIGITAL SIGNAL PROCESSOR 1st halfword 2nd halfword 1st half-word 2nd half-word • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005...
  • Page 90 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 HOST-PORT INTERFACE TIMING (CONTINUED) HCNTL[1:0] HR/W HHWIL HSTROBE † HD[15:0] (input) HRDY † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

  • Page 91: Multichannel Buffered Serial Port Timing

    CLKR ext CLKR int CLKR ext CLKX int CLKX ext CLKX int CLKX ext • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 GDPA−167 ZDPA−167 −200 UNIT −250 2P § 0.5 * t c(CKRX) −1 ¶...
  • Page 92 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) switching characteristics over recommended operating conditions for McBSP Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from t d(CKSH-CKRXH) CLKS input...
  • Page 93 FSR (int) FSR (ext) CLKX FSX (int) FSX (ext) FSX (XDATDLY=00b) Bit 0 POST OFFICE BOX 1443 FLOATING POINT DIGITAL SIGNAL PROCESSOR Bit(n-1) (n-2) Bit(n-1) (n-2) Figure 46. McBSP Timings • HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 (n-3) (n-3)
  • Page 94 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for FSR when GSYNC = 1 (see Figure 47) t su(FRH-CKSH) Setup time, FSR high before CLKS high t h(CKSH-FRH) Hold time, FSR high after CLKS high...
  • Page 95 Figure 48. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 FLOATING POINT DIGITAL SIGNAL PROCESSOR †‡ (see Figure 48) Bit(n-1) (n-2) Bit(n-1) (n-2) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 GDPA−167 ZDPA−167 −200 UNIT UNIT −250 MASTER § SLAVE T − 2 T + 3 L −...
  • Page 96 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED) timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0 t su(DRV-CKXH) Setup time, DR valid before CLKX high...
  • Page 97 ‡ For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. FLOATING POINT DIGITAL SIGNAL PROCESSOR Bit(n-1) (n-2) Bit(n-1) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 (n-3) (n-4) (n-2) (n-3) (n-4) †‡...
  • Page 98 TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 PARAMETER PARAMETER Hold time, FSX low t h(CKXH-FXL) after CLKX high ¶...
  • Page 99 Figure 51. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 FLOATING POINT DIGITAL SIGNAL PROCESSOR †‡ (see Figure 51) Bit(n-1) Bit(n-1) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 †‡ (see Figure 51) GDPA−167 ZDPA−167 −200 UNIT UNIT −250...

  • Page 100: Timer Timing

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 timing requirements for timer inputs t w(TINPH) Pulse duration, TINP high t w(TINPL) Pulse duration, TINP low † P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

  • Page 101: General-Purpose Input/Output (Gpio) Port Timing

    GPOx pulse width is 12P. GPIx GPOx FLOATING POINT DIGITAL SIGNAL PROCESSOR †‡ (see Figure 53) PARAMETER Figure 53. GPIO Port Timing • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 GDPA−167 ZDPA−167 −200 UNIT −250 †§ GDPA−167 ZDPA−167 −200 UNIT −250...

  • Page 102: Jtag Test-Port Timing

    TMS320C6711D FLOATING POINT DIGITAL SIGNAL PROCESSOR SPRS292 − OCTOBER 2005 timing requirements for JTAG test port (see Figure 54) t c(TCK) Cycle time, TCK t su(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high t h(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high...

  • Page 103: Mechanical Data

    FLOATING POINT DIGITAL SIGNAL PROCESSOR MECHANICAL DATA Two Signals, Two Planes (4-Layer Board) Two Signals, Two Planes (4-Layer Board) • POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443 TMS320C6711D SPRS292 − OCTOBER 2005 °C/W Air Flow (m/s) † °C/W Air Flow (m/s) †...

  • Page 104: Packaging Information

    www.ti.com PACKAGING INFORMATION Orderable Device Status TMS320C6711DGDP200 ACTIVE TMS320C6711DGDP250 ACTIVE TMS320C6711DZDP200 ACTIVE TMS32C6711DGDPA167 ACTIVE The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs.

  • Page 105: Mechanical Data

    GDP (S–PBGA–N272) 27,20 26,80 24,20 23,80 A1 Corner 1,22 1,12 0,90 0,65 0,60 0,57 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 24,13 TYP 1,27 Bottom View 2,57 MAX Seating Plane 0,10...
  • Page 106 ZDP (S–PBGA–N272) 27,20 26,80 24,20 23,80 A1 Corner 1,22 1,12 0,90 0,65 0,60 0,57 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MO-151 D. This package is lead-free. 24,13 TYP 1,27 Bottom View...

  • Page 107: Important Notice

    Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.

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