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is first performed in excess of URB until URC = H'3F. URC is not incremented by an LDTLB
instruction.
• SQMD: Store queue mode bit. Specifies the right of access to the store queues.
0: User/privileged access possible
1: Privileged access possible (address error exception in case of user access)
• SV: Bit that switches between single virtual memory mode and multiple virtual memory mode.
0: Multiple virtual memory mode
1: Single virtual memory mode
When this bit is changed, ensure that 1 is also written to the TI bit.
• TI: Writing 1 to this bit invalidates (clears to 0) all valid UTLB/ITLB bits. This bit always
returns 0 when read.
• AT: Specifies MMU enabling or disabling.
0: MMU disabled
1: MMU enabled
MMU exceptions are not generated when the AT bit is 0. In the case of software that does not
use the MMU, therefore, the AT bit should be cleared to 0.
3.3
Memory Space
3.3.1
Physical Memory Space
The SH7750 supports a 32-bit physical memory space, and can access a 4-Gbyte address space.
When the MMUCR.AT bit is cleared to 0 and the MMU is disabled, the address space is this
physical memory space. The physical memory space is divided into a number of areas, as shown
in figure 3.3. The physical memory space is permanently mapped onto 29-bit external memory
space; this correspondence can be implemented by ignoring the upper 3 bits of the physical
memory space addresses. In privileged mode, the 4-Gbyte space from the P0 area to the P4 area
can be accessed. In user mode, a 2-Gbyte space in the U0 area can be accessed. Accessing the P1
to P4 areas (except the store queue area) in user mode will cause an address error.
Rev. 2.0, 03/99, page 32 of 396
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