Configuration Diagram - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 35 Free-Run Timer
3.Configuration Diagram

3. Configuration Diagram

Free-run Timer
Count clock
CLK1-0 TCCS: bit 1-0
0 0 0 0 0 0 0 0 CLKP / 4 CLKP / 4
0 0 0 0
1 1 1 1 CLKP / 16 CLKP / 16
1 1 1 1 0 0 0 0 CLKP / 32 CLKP / 32
1 1 1 1 1 1 1 1
CLKP / 64 CLKP / 64
Peripheral clock
Divider
C LKP
External clock
Synchronization
External clock
CK /SCK/ Pxy.z
The clock selection
0 0
1 (Resource
output)
PFR/EPFR Function
0 0 0 0 0 0 0 0 General-purpose port
1
0 SCK (USART shift clock)
1 1
CK (FRT clock input)
Notes: When using the input/output (SCK), the external clock (CK) cannot be used because the port is shared.
Note: See "Chapter 24 Interrupt Control (Page
734
Figure 3-1 Configuration Diagram
STOP TCCS: bit 4
0
Count operation
1
Stop the count operation
0
Timer data register
1
circuit
OR
ECLK TCCS:bit 7
0
From the divider
1
From the outside
Read of the port
From the port
data register
CLR
GP DDRxy.z
0
0 Input only
1
Clears the timer
1
Enable output
Figure 3-2 Register List
Input capture
Count value
Overflow flag
IVF
TCDT
0
1
Interrupt request present
Clear WRITE 0: Flag clear
Count value
Output compare
1
0
TCCS:bit 2 MODE TCCS: bit 3
0 0
Disable the clear by the compare-match
No effect
1 1
Enable the clear by the compare-match
No.311)" about ICR register and interrupt vectors.
IVFE T CCS: bit 5
0
Disable interrupts
1
Enable interrupts
0
Free-run Timer
TCCS: bit 6
interrupt
No interrupt requests
1
The timer clear request by the
compare value match of the
output compare