Self Refresh - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 31 External Bus
9.SDRAM/FCRAM Interface Operation
MCLK
A
D
SRAS,SCAS,
SWE
• Setting TYP to 1001
READA/WRITA issuance to ACTV issuance is fixed at CL + BL - 1, however, TYP can be set to 1001
when FCRAM is connected.
• This timing is effective, for example, for recurring page misses as it eliminates the cycle for issuing the PRE
command.
■ Auto - refresh Operation Timing
Figure 9-5 shows auto - refresh operation timings.
MCLK
A
D
SRAS,SCAS,
SWE
• The refresh command is issued every " refresh control register's (RCR's) RFINT5 - RFINT0 value x 32 " cycles
and access is restarted upon completion of each refresh.
• Set the TRC bit in the refresh control register (RCR) according to the SDRAM/FCRAM standards.
• Satisfy the maximum RAS active time as well.

9.1 Self Refresh

This section describes self - refreshing.
584
Figure 9-4 Single Read/Write Timing Chart
Row Col Row
#1
ACTV WRITA ACTV
CL+BL-1
causes a read/write command with auto - precharge to be issued. Since the cycle from
B
Figure 9-5 Auto - refresh Timing Chart
REF
Col Row Col
#2 #3
READA ACTV WRITA
CL+BL-1
tRC
Refresh cycle
ACTV
only
B