Operation - Fujitsu MB91460 SERIES FR60 User Manual

32-bit microcontroller
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5. Operation

5.1 Subclock Oscillation Stability Wait Interrupt
Subclock
oscillation example
Clock timer
counting
(1)
10
2
Subclock stop bit
Operation clock mode
(1) Selects the interval (WS[1:0]) (In this example, 2
(2) Sets the timer so that it is cleared (WCL="0") by software.
(3) Sets the flag clear (WIF="0") and the interrupt request enable (WIE="1") by software.
(4) Sets the subclock stop release (OSCCR.OSCDS1="0") while the subclock is in operation by software.
(5) The subclock oscillation starts.
(6) Counts up with the subclock (source oscillation).
(7) Make the subclock oscillation stable.
(8) Makes the interval time be the selected time. (Detects the falling of 2
(9) If the flag (WIF) becomes "1", the subclock oscillation stability wait interrupt request is generated.
(10) Processing cause by an interrupt (Software): Switching the operation clock (Sub-RUN => main RUN)
(11) Interrupt request disable (WIE="0") and the interrupt request clear (WIF="0").
Figure 5-1 Reference
(5)
0400h
(6)
0000h
(Bit 9)
(4)
(2)
WCL
(3)
WIF
(3)
WIE
Subclock
Chapter 23 Sub Oscillation Stabilisation Timer
(7)
(8)
(8)
(11)
(9)
(11)
Main clock
(10)
10
/F
is selected.)
CL-SUB
10
dividing.)
5.Operation
Time
303

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