Table of Contents
Advertisement
Chapter 4 CPU Architecture
8.Word Alignment
8. Word Alignment
Since instructions and data are accessed by byte, allocated addresses vary by instruction length or
data width.
■ Program Access
FR60 program is required to be allocated in addresses multiplied by 2.
PC's bit0 is cleared for instruction execution upon the PC update.
(PC bit 0 may be set when odd address is specified for branching address, however, it is invalid. Since the
instruction is required to be allocated in addresses multiplied by 2, there is no odd address exception.)
■ Data Access
FR60 provides the following alignment for addresses depending on data width when executing data
access.
•
Word access
•
Half-word access : Address is multiplied by 2. (Lowest order bit is mandatorily 0.)
•
Byte access:
Upon the word and half-word data accesses, some bits mandatorily become 0 for computing results
of effective address. For example, in the case of addressing mode of @(R13, Ri), register value
before addition is used as is (even if lowest order bit is 1), and lower bits of addition results are
masked. Register values before computing are not masked.
[Example] LD @(R13, R2), R0
110
: Address is multiplied by 4. (Lowest order 2 bits are mandatorily 00.)
: Address is multiplied by 1.
R13
R2
+)
Addition results
00002225
00002224
Address pin
00002222
00000003
H
Lower 2 bits are
mandatorily masked.
H
Advertisement
Table of Contents
