Register Description - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 34 CAN Controller

2.Register Description

2. Register Description
This section lists the CAN registers and describes the function of each register in detail.
2.1 Programmer's Model
The CAN module allocates an address space of 256 bytes (64 words). The CAN registers can be accessed
from the CPU in byte, halfword and word.
The two sets of interface registers (IF1 and IF2) control the CPU access to the Message RAM. They buffer the
data to be transferred to and from the RAM, avoiding conflicts between CPU accesses and message
reception/transmission.
The data registers (IF1 Data and IF2 Data) are doubled in the address map, ordered both in little endian byte
and big endian byte.
If several CAN modules are present on a device then they are located linear in the address space with a
constant offset of 256 bytes (64 words). The base address of each CAN module is given by the following
table:
• Base-address of CAN0 :0x00C000
• Base-address of CAN1 :0x00C100
• Base-address of CAN2 :0x00C200
• Base-address of CAN3 :0x00C300
• Base-address of CAN4 :0x00C400
• Base-address of CAN5 :0x00C500
Address
+0
Base-addr +
0x00
bit[15:8]
reserved
Reset: 0x00
Base-addr +
0x04
bit[15:8]
RP,REC[6:0]
Reset: 0x00
Base-addr +
0x08
bit[15:8]
Int-Id[15:8]
Reset: 0x00
Base-addr +
0x0C
bit[15:8]
reserved
Reset: 0x00
692
+1
Control Register
bit[7:0]
see descr. CTRLR
Reset: 0x01
Error Counter
bit[7:0]
TEC[7:0]
Reset: 0x00
Interrupt Register
bit[7:0]
Int-Id[7:0]
Reset: 0x00
BRP Extension Register
bit[7:0]
BRP[3:0]
Reset: 0x00
Register
+2
Status Register
bit[15:8]
reserved
Reset: 0x00
Bit Timing Register
bit[15:8]
TSeg2[2:0],TSeg1[3:0]
Reset: 0x23
Test Register
bit[15:8]
reserved
Reset: 0x00
Reserved
bit[15:8]
reserved
Reset: 0x00
+3
bit[7:0]
see descr. STATR
Reset: 0x00
Error Counter is read
only.
bit[7:0]
Bit Timing Register
SJW[1:0],BRP[5:0]
is write enabled by
CCE
Reset: 0x01
Interrupt Register is
read only.
bit[7:0]
Test Register is write
see descr. TESTR
enabled by Test.
r signifies the actual
Reset: 0x00 &
value of the
0br0000000
CAN_RX pin.
BRP Extension Reg-
ister is write enabled
bit[7:0]
by CCE.
reserved
Reset: 0x00
Note