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Chapter 4
CPU Architecture
This chapter describes the architecture of FR60 family CPU.
1. Overview
The CPUs of the FR60 family series employ RISC architecture and advanced function instructions for
embedded application.
CPU of FR60 family employs Harvard architecture whose instruction bus and data bus are independent. "32-
bit/16-bit bus converter" realizes the interface between CPU and peripheral functions. "Harvard/Princeton bus
converter" connects both of I-bus and D-bus and realizes the interface between CPU and bus controller.
Embedded
Embedded
Flash or
I-Cache
ROM
F-Bus
Figure 1-1 Connection Diagram of Internal Architecture
I-Bus
Embedded
RAM
32
32
M-Bus
DMA
Controller
FR CPU
32
32
32
Harvard/Princeton
Bus Converter
32
32
32
X-Bus
Bus Converter
T-Bus
32
32
External Bus
Chapter 4 CPU Architecture
D-Bus
32
Bus Converter
32 <-> 16
R-Bus
13
16
16 bit
Resources
1.Overview
Embedded
RAM
32
32
32 bit
Resources
105
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