Explanations Of Registers - Fujitsu MB91460 SERIES FR60 User Manual

8. Explanations of Registers

● FLASH Interface Control Register
Control Register byte 0
Control Register byte 1
Control Register byte 2
Control Register byte 3
FLASH Memory Control and Status Register (FMCS)
• BIT[31]: ASYNC - ASYNChronous access enable
0 Synchronous FLASH access (default)
1 Asynchronous FLASH access
The ASYNC bit is cleared at reset, which enables the fast synchronous FLASH access mode by default. To switch
to asynchronous mode, set this bit (however it is basically not recommended to set this bit, neither in read nor in
write access).
• BIT[30]: FIXE - FIXed reset and mode vector Enable
0 Disable FMV/FRV and enable FLASH access at mode vector address
1 Output the fixed mode or reset vector at address hit (default)
The FIXE bit is set by default.
To enable FLASH access on address 0x000ffff8 and 0x000ffffc, clear this bit.
31
ASYNC
Address : 7000
H
Read/write ⇒ (R/W) (R/W) (R/W) (R)
(0)
Default value⇒
23
Address : 7001
H
-
Read/write ⇒
(-)
(X)
Default value⇒
15
Address : 7002
H -
Read/write ⇒
(-)
(X)
Default value⇒
7
Address : 7003
H
FLUSH (DBEN) PFEN PFMC
Read/write ⇒
(R/W) (R /W ) (R /W ) (R /W ) (R/W) (R/W) (R/W) (R/W)
(1)
Default value⇒
30 29 28 27
(BIRE) RDYEG
FIXE RDY
(R) (R/W) (R/W) (R/W)
(1) (1) (0) (1)
22 21 20 19
- - - LOCK PHASE
(-) (-) (-) (R/W) (R/W) (R/W) (R/W)
(X) (X) (X) (0)
14 13 12 11
- - - -
(-) (-) (-) (-)
(X) (X) (X) (X)
6 5 4 3
LOCK
(0) (0) (0) (0)
Chapter 11 Memory Controller
8.Explanations of Registers
⇐ Bit no.
26 25 24
RDYI RW16 LPM
(0) (0) (0)
⇐ Bit no.
18 17 16
PF2I RD64
(0) (0) (0)
⇐ Bit no.
10 9 8
- REN (TAGE)
(-) (R/W) (R/W)
(X) (0) (0)
⇐ Bit no.
2 1 0
ENAB SIZE1 SIZE0
(0) (1) (1)
FMCS
FMCR
FCHCR
FCHCR
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