Register - Fujitsu MB91460 SERIES FR60 User Manual

32-bit microcontroller
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Chapter 41 Up/Down Counter

4.Register

4. Register
4.1 UDCC: Counter Control Register
This register is used to control behaviors of Up/Down Counter.
• UDCC0 (Up/Down Counter 0): Address 0304
• UDCC1 (Up/Down Counter 1): Address 0308
• UDCC2 (Up/Down Counter 2): Address 0314
• UDCC3 (Up/Down Counter 3): Address 0318
15
14
M16E/
CDCF
Reserved
0
0
R/W *
R/W
7
6
Reserved
CTUT
0
0
R/W0
R/W
(For attributes, refer to
bit15: Enable 16 bit mode (Up/Down Counter
M16E
8 bit × 2 channel operation mode (8 bit mode)
0
16 bit × 1 channel operation mode (16 bit mode)
1
* Reserved bit (Up/Down Counter 1 and 3). Be sure to write 0. The read value is the value written.
• bit14: Count direction change flag (Interrupt request flag)
CDCF
0
A direction change has not made.
1
Direction change has been made once or more.
• When the count direction has been changed during count operation, the count direction change flag
(CDCF) is set to "1".
• Since the count direction is set to countdown immediately after a reset, the count direction change flag
(CDCF) is set to "1" on counting up following the reset.
• To enable interrupt requests, the interrupt request permission bit must be set (CFIE="1").
• bit13: Enable count direction change interrupt request
CFIE
0
Disable direction change interrupt requests.
1
Enable direction change interrupt requests.
When the interrupt request permission bit is set to "1", the interrupt request flag (CDCF) is enabled.
• bit12: Select internal prescaler
CLKS
F
/2
0
CLKP
F
/8
1
CLKP
840
13
12
11
CFIE
CLKS
CMS1
0
0
0
R/W
R/W
R/W
5
4
3
UCRE
RLDE
UDCLR
0
0
1
R/W
R/W
R1,W
"Meaning of Bit Attribute Symbols (Page
0
Direction change detection
When read:
Direction change interrupt request
(Access:
Byte, Half-word
H
(Access:
Byte, Half-word
H
(Access:
Byte, Half-word
H
(Access:
Byte, Half-word
H
10
9
CMS0
CES1
0
0
R/W
R/W
2
1
CGSC
CGE1
0
0
R/W
R/W
No.10)".)
only)
Enable 16 bit mode
Clear the flag.
Writing does not affect the operation.
Internal clock frequency
)
)
)
)
8
bit
CES0
UDCCH
0
Initial value
R/W
Attribute
0
bit
CGE0
UDCCL
0
Initial value
R/W
Attribute
When written:

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