Fujitsu MB91460 SERIES FR60 User Manual page 712

Chapter 34 CAN Controller
2.Register Description
Additionally the busoff state is reset and the output CAN_TX is set to recessive(HIGH). The value 0x0001 (Init
= '1') in the CAN Control Register enables the software initialisation. The CAN does not influence the CAN bus
until the CPU resets Init to '0'.
The data stored in the Message RAM is not affected by a hardware reset. After power-on, the contents of the
Message RAM is undefined.
2.3 CAN Protocol Related Registers
These registers are related to the CAN protocol controller in the CAN Core. They control the operating modes
and the configuration of the CAN bit timing and provide status information.
■ CAN Control Register (CTRLR)
CAN Control Register high byte
Address : Base + 0x00
CAN Control Register low byte
Address : Base + 0x 01
696
15
res
H
Read/write ⇒
(R)
(0)
Default value⇒
7
Test CCE DAR
H
Read/write ⇒
(R/W) (R/W) (R/W) (R)
(0)
Default value⇒
14 13 12 11
res res res res
(R) (R) (R) (R)
(0) (0) (0) (0)
6 5 4 3
res EIE
(R/W) (R/W) (R/W) (R/W)
(0) (0) (0) (0)
⇐ Bit no.
10 9 8
res res res
(R) (R) (R)
(0) (0) (0)
⇐ Bit no.
2 1 0
SIE IE Init
(0) (0) (1)
CTRLRH
CTRLRL