Chapter 23 Sub Oscillation Stabilisation Timer; Overview; Features - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 23 Sub Oscillation Stabilisation Timer

1. Overview

The sub oscillation stabilisation timer is a 15-bit counter that is counted up with the subclock. This timer does
not affect the selection/dividing setting of the MCU operating clock.
This timer is used to acquire subclock oscillation stability wait time if the subclock oscillation is resumed mainly
when the subclock oscillation is stopped while the main clock is in operation.
This timer is can be used for acquiring sub clock oscillation stability wait time to resume sub clock oscillation
after the sub clock oscillation has been stopped (OSCCR.OSCDS2=1) while the RC oscillator is being
operated.
Sub clock
(Source oscillation)

2. Features

• Type : 15-bit free run counter
• Quantity : 1
• Clock source : Subclock (source oscillation) --- Period = 1/F
• Interval time : 4 types
• Timer clear cause: (Software, overflow, reset (INIT))
• Interrupt : clock interrupt (interval interrupt)
• Count value : Cannot read and write (Clear only)
Up-counter
10
Period = 2 /F , 2
CL-SUB
(31.25ms, 0.25s, 0.50s, 1.00s)
Chapter 23 Sub Oscillation Stabilisation Timer
Selector
CL-SUB
13 14
/F , 2 /F
CL-SUB CL-SUB
Interrupt
= 1/32.768kHz
15
, 2 /F ,
CL-SUB
1.Overview
299