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8. Caution
• The main PLL needs the PLL lock wait time after operation enable and after modifying the rate of multiply.
We recommend that this main PLL lock wait time be acquired using the timebase interrupt.
The lockup time of PLL is approximately 600us. Make sure that the PLL lock wait time is set to a value a
little larger than 600us.
• Regarding the interval setting
• When modifying the timebase timer interval time, set the interrupt request enable bit (TBIE) to "0" in
advance to disable an interrupt.
• The timebase counter is always counting. Clear the timebase counter before enabling an interrupt to
acquire an accurate interval interrupt time using the timebase timer.
(If not, an interrupt request may be generated immediately after an interrupt enable.)
• About clearing the timebase counter using a program
• If you write data in the timebase counter clear register CTBR in the order of "A5
timebase counter is cleared immediately after writing "5A
• Although there are no restrictions on the write timings for "A5
other than "5A
written.
• If the timebase counter is cleared, the reset signal to the watchdog is generated with a delay once.
• About clearing the timebase counter by the hardware
The timebase counter is cleared by the STOP mode and the setting initialization reset (INIT pin input,
watchdog reset). (All bits are "0.")
• In the stop mode
When returning to the interrupt from a stop, the timebase counter is used to acquire the clock oscillation
stability wait time. As a result, there is a possibility to unintentionally generate timebase timer's interval
interrupt. Therefore, disable the timebase timer interrupt not to use the timebase timer before the stop is set.
" the clearing operation is not performed if "A5
H
Chapter 19 Timebase Timer
". (All bits are "0.")
H
" and "5A
" writing "A5
H
H
" is not written again even if "5A
H
8.Caution
" and "5A
" the
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H
" followed by a one
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" is
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