Register - Fujitsu MB91460 SERIES FR60 User Manual

3. Register

3.1 Hardware watchdog timer control and status register
Hardware watchdog timer control status register (with reset flag and clear bit).
• HWWD: Address 04C7h (Access: Byte)
7 6
RESV0 RESV0
0 0
0 0
R/W0 R/W0
(See "Meaning of Bit Attribute Symbols (Page
• Bit7-5: Reserved bits. Always write "0" to these bits.
• Bit4: Reserved bit. Always write "1" to this bit.
• Bit3: CL (counter clear).
CL
0
1
This bit is write only, it is always read as '1'.
• Bit2-1: Reserved bits. Always write "0" to these bits.
• Bit0: CPUF (CPU reset Flag).
CPUF
0
1
This bit is initialized by external reset input (INITX) or clock supervisor reset, but not by internal reset.
Writing '0' clears this bit, writing '1' has no effect.
5 4 3
RESV0 RESV1 CL
0 1 1
0 1 1
R/W0 R/W1 W
By writing '0' the watchdog timer is cleared
Writing '1' has no effect
Watchdog reset not triggered
Watchdog reset triggered (overflow of watchdog timer occured)
2 1
RESV0 RESV0
0 0
0 0
R/W0 R/W0
No.10)" for details of the attributes.)
Function
Function
Chapter 21 Hardware Watchdog Timer
0 bit
CPUF
Initial value (
INIT pin input,
0
watchdog reset
Initial value
X
(Software reset)
R/W Attribute
3.Register
)
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