Operating Mode Conditions - Fujitsu MB91460 SERIES FR60 User Manual

3. Operating mode conditions

● Cache status in various operating modes
The table below indicates the prevailing state for disable and flush when the associated bit is
changed by bit manipulation instruction, etc.
Cache Memory
Tag Address
Tag
Sub-block
Valid Bit
LRU Bit
Entry Lock
Bit
TAG Valid
Bit
RAM
Control Global
Register Lock
Auto lock
Fail
Entry Auto
Lock
Entry Lock
Release
Enable
Flush
Immediately
after a Reset
Contents The preceding state is held.
undefined Rewriting is impossible while
the cache is disabled.
Contents The preceding state is held.
undefined
Rewriting is impossible while
the cache is disabled.
Contents The preceding state is held.
undefined Rewriting is impossible while
the cache is disabled.
Contents The preceding state is held.
undefined Rewriting is impossible while
the cache is disabled.
Contents The preceding state is held.
undefined Rewriting is impossible while
the cache is disabled.
Contents The preceding state is held.
undefined Flushingis possible while the
cache is disabled.
Normal Mode The preceding state is held.
Flushing is possible while
the cache is disabled.
Unlock The preceding state is held.
Rewriting is possible while
the cache is disabled.
No fail The preceding state is held.
Rewriting is possible while
the cache is disabled.
Unlock The preceding state is held.
Rewriting is possible while
the cache is disabled.
No release The preceding state is held.
Rewriting is possible while
the cache is disabled.
Disable Disabled
Not flushed The preceding state is held.
Rewriting is possible while
the cache is disabled.
Disable (FNAB=0)
Chapter 12 Instruction Cache
3.Operating mode conditions
Flushed
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
(entry lock release is required)
All entries are invalid.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
The preceding state is held.
Flushed in cycle following
memory accessing.
Reverts to 0 subsequently.
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