Registers - Fujitsu MB91460 SERIES FR60 User Manual

4. Registers

4.1 STCR: Standby Control Register
Controls transition to standby modes, pin states during stop mode, whether to halt the clock during stop mode,
the oscillation stabilization wait time, and software reset.
Note: See also "Chapter 10
No.273)" chapters.
• STCR: Address 0481h (Access: Byte)
7 6
STOP SLEEP HIZ
0 0
0 0
0 0
R/W R/W R/W
(See "Meaning of Bit Attribute Symbols (Page
• Bit7: Stop mode (STOP)
• Setting "1" changes to stop mode.
• Bit6: Sleep mode (SLEEP)
• Setting "1" changes to sleep mode.
• If this bit and the stop mode bit (STOP) bit are set to "1" at the same time, the device goes to stop mode.
• Bit5: High impedance mode (HIZ)
• Setting "0" specifies that pins maintain the same states they have on entering stop mode.
• Setting "1" specifies that pin outputs go to high impedance (Hi-z) during stop mode.
• Bit4: Software reset (SRST)
• Setting "0" triggers a software reset.
• Note that negative logic is used.
• Bit3-2: Oscillation stabilization time selection
The oscillation stabilization wait time after a reset (INIT) or on recovering from stop mode.
OS[1:0]
stabilization
00
01
10
11
• F2: Main clock divided by two or subclock
• In the case of a reset triggered by an INIT pin input, operation defaults to "00" (F2 x 2
• In the case of other resets or on recovering from stop mode, the specified clock (main or sub) and
oscillation stabilization wait time (OS[1:0]) are used.
• The count is performed by the timebase counter.
• Bit1: Sub clock oscillation halt (OSCD2)
Setting "1" specifies that the sub clock oscillation halts in stop mode.
• bit0: Main clock oscillation halt (OSCD1)
Setting "1" specifies that the main clock oscillation halts in stop mode.
(See "8. Caution (Page
Standby (Page
5 4 3
SRST OS1
1 1 0
1 1 X
X 1 X
R1,W R/W
Oscillation
When using main clock
(For a 4.0MHz main clock)
wait time
Φ2 × 2 1
Φ2 × 2 11
Φ2 × 2 16
Φ2 × 2 22
No.262)".)
No.155)" and "Chapter 20
2 1 0
OS0 OSCD2 OSCD1
0 1 1
X 1 1
X X X
R/W RX,W R/W
No.10)" for details of the attributes.)
1.00µs
1.0ms
32ms
2s
Chapter 18 Timebase Counter
Software Watchdog Timer (Page
bit
Initial value
(INITX pin input)
Initial value (Watchdog)
Initial value (Software reset)
Attribute
When using subclock
(For a 32.768kHz subclock)
61µs
62.5ms
2.0s
128s
1
4.Registers
, main clock).
251