Usart Interrupts - Fujitsu MB91460 SERIES FR60 User Manual

Chapter 32 USART (LIN / FIFO)

5.USART Interrupts

5. USART Interrupts
The USART uses both reception and transmission interrupts. An interrupt request can be generated for either
of the following causes:
• Receive data is set in the Reception Data Register (RDR04), or a reception error occurs.
• Transmission data is transferred from the Transmission Data Register (TDR04) to the transmission shift
register.
• A LIN break is detected
• No bus activity (neither reception nor transmission)
■ USART Interrupts
Table 5-1 Interrupt control bits and interrupt causes of USART
Reception/
Interrupt
transmission/
request
ICU
flag bit
Reception RDRF
ORE
FRE
PE
LBD
TBI &
RBI
Transmission TDRE
Input ICP4
Capture Unit
ICP4
x : Used
* : Only available if ECCR04/SSM = 1
■ Reception Interrupt
If one of the following events occur in reception mode, the corresponding flag bit of the Serial Status Register
(SSR04) is set to "1":
• - Data reception is complete, i. e. the received data was transferred from the serial input shift register to the
Reception Data Register (RDR04) and data can be read: RDRF (if FIFO is enabled, trigger level is reached)
• - Overrun error, i. e. RDRF = 1 and RDR04 was not read by the CPU: ORE
638
Operation
Flag mode
Register
0 1 2
SSR04 x x x
SSR04 x x x
SSR04 x x *
SSR04 x *
ESCR04 x
ESCR04 x x
SSR04 x x x
IPCP4 x
IPCP4 x
Interrupt
cause
3
x receive data is
written to RDR
(FIFO level reached)
x Overrun error
x Framing error
Parity error
x LIN synch break
detected
x no bus activity
x Empty transmission
register
x 1st falling edge of
LIN synch field
x 5th falling edge of
LIN synch field
Interrupt How to clear
cause the Interrupt
enable bit Request
SSR04 : Receive data
RIE is read
"1" is written to
clear rec. error
bit (SCR04:
CRE)
ESCR04 : "0" is written to
LBIE ESCR04 : LBD
ECCR04 : Receive data /
BIE Send data
SSR04 : Transfer data is
TIE written
IPCP4 : disable ICE4
ICE4 temporary
IPCP4 : disable ICE4
ICE4