Register - Fujitsu MB91460 SERIES FR60 User Manual

4. Register

4.1 TBCR: Timebase Timer Control Register
This register is used to set timebase timer interrupt control, reset/ standby operation option etc.
Note: Refer also to "Chapter 10 Standby (Page
• TBCR: Address 0482h (Access: Byte)
7 6
TBIF TBIE
0 0
0 0
R(RM1),W R/W
(Refer to "Meaning of Bit Attribute Symbols (Page
• Bit7: Timebase timer interrupt request flag
TBIF
0
1 (The interval time set by the timebase timer
• An interrupt request is generated if the timebase timer interrupt request enable bit is "1", and if the
timebase timer interrupt request flag is "1".
• Bit6: Timebase timer interrupt request enable
TBIE
0
1
• Bit5-3: Selecting the timebase timer interval time
TBC2-TBC0
000
001
010
011
100
101
110
111
• Be sure to set the interval time before an interrupt.
(Oscillation stability wait time used when returning to the stop caused by an interrupt)
• Bit2: Reserved bit
Writing does not affect the operation. The read value is indefinite.
5 4 3
TBC2 TBC1 TBC0
X X X
X X X
R/W R/W R/W
Read
With no interrupt request
With interrupt request
has elapsed)
Disabling the timebase timer interrupt request
Enabling the timebase timer interrupt request
Interval time
Φ × 2 11
Φ × 2 12
Φ × 2 13
Φ × 2 22
Φ × 2 23
Φ × 2 24
Φ × 2 25
Φ × 2 26
No.155)".
2 1
--- SYNCR
X 0
X X
RX/WX RX/WX
No.10)" for the attributes.)
Operation
Writing does not affect operation
Operation
While the main clock operates
(4.0MHz, PLL8 multiply)
µ
64.0 s
µ
128 s
µ
256 s
131ms
262ms
524ms
1048ms
2097ms
Chapter 19 Timebase Timer
0 bit
SYNCS
Initial value
0 (INIT terminal input,
watchdog reset)
Initial value
X
(the software reset)
R/W Attribute
Write
Flag is cleared
Example
While the subclock operates
(32.768kHz)
62.5ms
125ms
250ms
128s
256s
512s
1024s
2048s
4.Register
265