Registers - Fujitsu MB91460 SERIES FR60 User Manual

32-bit microcontroller
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Chapter 15 CAN Clock Prescaler

3.Registers

3. Registers
3.1 CAN Clock Control Register
Controls the CAN clock source, the clock division ratio and the clock disable.
• CANPRE: Address 04C0h (Access: Byte)
7
6
-
-
0
0
0
0
R0/W0
R0/W0
(See
"Meaning of Bit Attribute Symbols (Page
• Bit7-6: Reserved bitAlways write "0" to these register bits.
• Bit5-4: CAN Prescaler ClocK Selection
CPCKS1-CPCKS0
00
01
10
11
• Bit3-0: Source clock Divide-by-C selection
DVC3-DVC0
0000
0001
0010
0011
0100
0101
0110
0111
......
1111
(Note)
Do not exceed the specified upper frequency limit of CANCLK (e.g. 20 MHz) e.g. by setting prescaler
values exceeding this limit, or by switching the prescaler clock source to a higher frequency clock
without switching previously the prescaler values to higher division rates.
(Note)
If prescaler source is selected to PLL output: Even though it is possible to select no division ratio (:1)
for the divide-by-C counter it is not recommended. The resulting output clock will have an odd clock
duty ratio (direct PLL output can have up to 90:10 duty). Always select at least a division ratio > 1.
• CANCKD: Address 04C1h (Access: Byte)
7
6
-
-
CANCKD5 CANCKD4 CANCKD3 CANCKD2 CANCKD1 CANCKD0
0
0
218
5
4
3
CPCKS1 CPCKS0
DVC3
0
0
0
X
X
X
R/W
R/W
R/W
Source clock divided-by-C (generates CANCLK)
5
4
0
0
2
1
DVC2
DVC1
0
0
X
X
R/W
R/W
No.10)" for details of the attributes.)
Prescaler clock source
CLKB, core clock (inital)
PLL output
reserved
Main oscillation
Source clock : 1 (no division)
Source clock : 2 (division by 2)
Source clock : 3 (division by 3)
Source clock : 4 (division by 4)
Source clock : 5 (division by 5)
Source clock : 6 (division by 6)
Source clock : 7 (division by 7)
Source clock : 8 (division by 8)
.....
Source clock : 16 (division by 16)
3
2
0
0
0
bit
DVC0
Initial value (
INIT pin input,
0
watchdog reset
Initial value
X
(Software reset)
R/W
Attribute
1
0
Initial value (
0
0
)
bit
INIT pin input,
)
watchdog reset

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