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Chapter 26 DMA Controller
3.DMA Controller (DMAC) Operation
3. DMA Controller (DMAC) Operation
A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-func-
tional DMAC that controls data transfer at high speed without the use of CPU instructions.
This section describes the operation of the DMAC.
■ Principal Operations
•
Functions can be set for each transfer channel independently.
•
Once starting has been enabled, a channel starts transfer operation only after a specified transfer request has
been detected.
•
After a transfer request is detected, a DMA transfer request is output to the bus controller and the bus right is
acquired by the bus controller before the transfer is started.
•
The transfer is carried out as a sequence conforming to the mode settings made independently for the
channel being used.
■ Transfer Mode
Each DMA channel performs transfer according to the transfer mode set by the MOD[1:0] bits of its DMACB
register.
● Block/step transfer
Only a single block transfer unit is transferred in response to one transfer request. DMA then stops requesting the
bus controller for transfer until the next transfer request is received.
The block transfer unit is the specified block size (BLK[3:0] of DMACA).
● Burst transfer
Transfer in response to one transfer request is carried out continuously for the number of times in the specified
transfer count is reached.
The specified transfer count is the transfer count (BLK[3:0] of DMACA X DTC[15:0] of DMACA) X block size.
● Demand transfer
Transfer is carried out continuously until the transfer request input (detected with a level at the DREQ pin) from
an external device or a specified transfer count is reached.
The specified transfer count in a demand transfer is the specified transfer count (DTC[15:0] of DMACA). The
block size is always 1 and the register value is ignored.
■ Transfer Type
● 2-cycle transfer (normal transfer)
The DMA controller operates using a read operation and a write operation as its unit of operation.
Data is read from an address in the transfer source register and then written to another address in the transfer
destination register.
● Fly-by transfer (memory --> I/O)
The DMA controller operates using a read operation as its unit of operation.
If DMA transfer is performed when fly-by transfer is set, DMA issues a fly-by transfer (read) request to the bus
controller and the bus controller lets the external interface carry out the fly-by transfer (read).
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