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Chapter 18 Timebase Counter
8.Caution
8. Caution
• Clock source
If the clock selected as the clock source is not stable, an oscillation stabilization wait time is required.
• Oscillation stabilization wait time
The wait time set in the oscillation stabilization time selection bits (STCR.OS[1:0]) is not initialized by any
reset except a reset triggered by the external INITX pin input, the RC based watchdog or the Clock
Supervisor. For other resets including settings initialization resets (timebase counter based watchdog reset)
and operation initialization resets (RST), the wait time set prior to the reset is used.
• Watchdog reset (Timebase Counter based watchdog)
Although an oscillation stabilization wait time is not required if a watchdog reset occurs while the main clock
is running (main or sub), a wait time is generated automatically. In this case, the oscillation stabilization wait
time (STCR.OS[1:0]) is not initialized.
• "L" level input to INIT pin
As the oscillation stabilization wait time is initialized to its minimum value when an initialization is triggered
by an INIT pin input, the wait time in this case is too short. Ensure the INIT pin input width is long enough to
provide the oscillation stabilization wait time.
In the following three cases, maintain the INIT pin input at the "L" level for long enough to provide the
oscillation stabilization wait time required by the oscillation circuit.
• INIT pin input after turning on the power
• INIT pin input after oscillation halted in stop mode
• INIT pin input when subclock selected as the clock source and main clock oscillation halted
(Accordingly, to stabilize the oscillation of both the main and subclocks, input an "L" level to the INIT pin for
long enough to provide a sufficient oscillation stabilization time for both the main and subclocks.)
• Main PLL lock wait
If enabling the main PLL from the halted state after program execution starts, the main PLL must not be
used until after sufficient time has elapsed for the main PLL to lock.
Similarly, when changing the multiplier setting for the main PLL when the PLL is running, the new main PLL
clock must not be used until sufficient time has elapsed for the main PLL to lock.
Using the timebase timer interrupt to generate the main PLL lock wait time is recommended.
• Cases when oscillation stabilization wait is not required
Although no oscillation stabilization wait is required when recovering via an interrupt from main stop or sub
stop mode when the main clock oscillation has not been halted, the oscillation stabilization wait is generated
automatically. Setting the wait time to its minimum value prior to entering stop mode is recommended.
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