Registers - Fujitsu MB91460 SERIES FR60 User Manual

4. Registers

4.1 ELVR: Interrupt Request Level Register
The register that selects request detection of external interrupts.
• ELVR0 (INT0-INT7): Address 032H (access: Half-word, Word)
15 14
LB7 LA7
0 0
R/W R/W
7 6
LB3 LA3
0 0
R/W R/W
(About attributes, see
• ELVR1 (INT8-INT15): Address 036H (access: Half-word, Word)
15 14
LB15 LA15
0 0
R/W R/W
7 6
LB11 LA11
0 0
R/W R/W
(About attributes, see
Interrupt request level bits (LBn, LAn) are registers that select request detection.
2 bits (LBn, LAn) are assigned to each external interrupt INTn.
LBn LAn
0 0 Detect "L" level and generate an interrupt request.
0 1 Detect "H" level and generate an interrupt request.
1 0 Detect the rise and generate an interrupt request.
1 1 Detect the fall and generate an interrupt request.
When the request input is a level (LAn, LBn = "00" or "01"), and when the INTn pin input is the valid level, the
corresponding bit (ERn) will be re-set to "1" even if the external interrupt request bit (ERn) is set to "0".
Note: n = 0 to 15
13 12 11
LB6 LA6 LB5
0 0 0
R/W R/W R/W
5 4 3
LB2 LA2 LB1
0 0 0
R/W R/W R/W
"Meaning of Bit Attribute Symbols (Page
13 12 11
LB14 LA14 LB13
0 0 0
R/W R/W R/W
5 4 3
LB10 LA10 LB9
0 0 0
R/W R/W R/W
"Meaning of Bit Attribute Symbols (Page
10 9
LA5 LB4
0 0
R/W R/W
2 1
LA1 LB0
0 0
R/W R/W
No.10)".)
10 9
LA13 LB12 LA12
0 0
R/W R/W
2 1
LA9 LB8
0 0
R/W R/W
No.10)".)
Description
Chapter 25 External Interrupt
8 Bit
LA4
0 Initial value
R/W Attribute
0 Bit
LA0
0 Initial value
R/W Attribute
8 Bit
0 Initial value
R/W Attribute
0 Bit
LA8
0 Initial value
R/W Attribute
4.Registers
325