Toshiba H1 Series Data Book page 748

(22) I S (2/2)
2
Symbol Name
Address
1808H
I2S
I2S0CTL Control
Register0
1809H
180AH
I2S0
Divider
I2S0C Value
Setting
Register
180BH
1818H
I2S
I2S1CTL Control
Register1
1819H
181AH
I2S1
Divider
I2S1C Value
Setting
Register
181BH
7 6 5
TXE0 *CNTE0
R/W R/W
0 0
Transmit Counter
control
0: Stop
0: Clear
1: Start
1: Start
CLKS0
R/W
0
Source
clock
0: f
SYS
1: f
PLL
CK07 CK06 CK05
0 0 0
Divider value for CK signal (8-bit counter)
WS05
0
TXE1 *CNTE1
R/W R/W
0 0
Transmit Counter
control
0: Stop
0: Clear
1: Start
1: Start
CLKS1
R/W
0
Source
clock
0: f
SYS
1: f
PLL
CK17 CK16 CK15
0 0 0
Set divide frequency for CK signal (8-bit counter)
WS15
0
92CZ26A-745
4 3
DIR0 BIT0 DTFMT01 DTFMT00 SYSCKE0
R/W R/W R/W
0 0
Transmis Bit length Output format
sion start
00: I2S
BIT
10: Right
0: 8 bits
0:MSB
01: Left
1:16 bits
1:LSB
11:Reserved
FSEL0 TEMP0 WLVL0
R/W R R/W
0 1
Stereo WS level
Condition of
transmission
/monaural
FIFO
0: Stereo 0:low left
0: data
1: Monaural 1:high left
1: None
data
CK04 CK03 CK02
R/W
0 0
WS04 WS03 WS02
R/W
0 0
Divider value for WS signal (6-bit counter)
DIR1 BIT1 DTFMT11 DTFMT10 SYSCKE1
R/W R/W R/W
0 0
Transmis Bit length Output format
sion start
00: I2S
BIT
Right
0: 8 bits
0:MSB
01: Left
1:16 bits
1:LSB
FSEL1 TEMP1 WLVL1
R/W R R/W
0 1
Stereo WS level
Condition of
transmission
/monaural
FIFO
0: Stereo 0:low left
0: data
1: Monaural 1:high left
1: None
data
CK14 CK13 CK12
R/W
0 0
WS14 WS13 WS12
R/W
0 0
Set divided frequency for WS signal (6-bit counter)
TMP92CZ26A
2 1 0
R/W R/W
0 0 0
System
clock
0:Disable
1:Enable
EDGE0 CLKE0
R/W R/W
0 0 0
Clock Clock
edge for enable
data
(After trans-
output
mission)
0:Rising
0:Operate
1:Falling
1:Stop
CK01 CK00
0 0 0
WS01 WS00
0 0 0
R/W R/W
0 0 0
System
clock
10:
0:Disable
1:Enable
11:Reserved
EDGE1 CLKE1
R/W R/W
0 0 0
Clock Clock
edge for enable
data
(After trans-
output
mission)
0:Rising
0:Operate
1:Falling
1:Stop
CK11 CK10
0 0 0
WS11 WS10
0 0 0