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ADREG4L
bit Symbol
(12A8H)
Read/Write
After reset
Function
bit Symbol
ADREG4H
(12A9H)
Read/Write
After reset
Function
bit Symbol
ADREG5L
(12AAH)
Read/Write
After reset
Function
bit Symbol
ADREG5H
(12ABH)
Read/Write
After reset
Function
Channel X conversion result
•
Bits 5 ∼ 2 are always read as "0".
•
Bit 0 is the AD conversion result store flag <ADRxRF>. When AD conversion result is stored, the flag is set to "1".
When Lower register (ADRECxL) is read, this bit is cleared to "0".
•
Bit 1 is the Overrun flag <OVRx>. This bit is set to "1" if a next conversion result is written to the ADREGxH/L
before both the ADREGxH and ADREGxL are read. This bit is cleared to "0" by reading Flag.
AD Conversion Result Register 4 Low
7
6
5
ADR41
ADR40
R
0
0
Store Lower 2 bits of
AN4 AD conversion
result
AD Conversion Result Register 4 High
7
6
5
ADR49
ADR48
ADR47
0
0
0
Store Upper 8 bits of AN4 AD conversion result
AD Conversion Result Register 5 Low
7
6
5
ADR51
ADR50
R
0
0
Store Lower 2 bits of
AN5 AD conversion
result
AD Conversion Result Register 5 High
7
6
5
ADR59
ADR58
ADR57
0
0
0
Store Upper 8 bits of AN5 AD conversion result
9
8
7
6
ADREGxH
7
6
5
4
Figure 3.23.8 AD Conversion Registers
92CZ26A-602
4
3
4
3
ADR46
ADR45
R
0
0
4
3
4
3
ADR56
ADR55
R
0
0
5
4
3
2
1
0
3
2
1
0
7
6
TMP92CZ26A
2
1
0
OVR4
ADR4RF
R
R
0
0
Overrun flag
AD conversion
result store
0:No generate
flag
1: Generate
1: Stored
2
1
0
ADR44
ADR43
ADR42
0
0
0
2
1
0
OVR5
ADR5RF
R
R
0
0
Overrun flag
AD conversion
result store
0:No generate
flag
1: Generate
1: Stored
2
1
0
ADR54
ADR53
ADR52
0
0
0
ADREGxL
5
4
3
2
1
0
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