Toshiba H1 Series Data Book page 536

The enable width of the LLOAD signal is specified using LCDLDW<LDW9:0>. It can
be set in a range of 0 to 1024 pulses of the LCP0 clock.
The actual enable width is determined depending on the LCDLDDLY<PDT> setting,
as shown below.
Enable width = <LDW9:0> + 1 (when <PDT> = 1, <LDW9:0>=0 is prohibited)
Enable width = <LDW9:0>
LCDLDW bit Symbol
(0295H)
Read/Write
After reset
Function
LCDHWB8
bit Symbol
(0299H)
Read/Write
After reset
LGOE2 width (bits 9-8) LGOE1 width (bits 9-8)
Function
When LCDCTL0<LCP0OC>=1, the enable width of the LLOAD signal is shown
below.
LLOAD
LCDLDDLY<PDT> = 0
LLOAD
LCDLDDLY<PDT> = 1
LCP0
LD23-LD0
7 6 5
LDW7 LDW6 LDW5
0 0 0
7 6 5
O2W9 O2W8 O1W9
0 0 0
(when <PDT> = 0)
LCDLDW Register
4 3
LDW4 LDW3
W
0 0
LLOAD width (bits 7-0)
4 3
O1W8 O0W8
W
0 0
LGOE0
width
(bit 8)
92CZ26A-533
TMP92CZ26A
2 1
LDW2 LDW1 LDW0
0 0
2 1
LDW9 LDW8 HSW8
0 0
LLOAD width (bits 9-8) LHSYNC
width
(bit 8)
0
0
0
0