Toshiba H1 Series Data Book page 262

3. Read
Reading valid data
; ***** Read valid data*****
;
ldw
ldw
ld
ldw
ld
;
; Wait setup time (from Busy to Ready)
;
;
;
ldw
ld
ldw
ld
ld
ld
ld
Generating ECC → Reading ECC
; ***** Read ECC *****
;
ldw
ldw
;
ldw
;
ldw
;
ldw
;
Software processing
The ECC data generated for the read operation and the ECC in the
redundant area in the NAND Flash are compared. If any error is found, the
error processing routine is performed to correct the error data. For details,
see 3.11.3.2 "Error Correction Methods".
(ndfmcr0),2010h ; CE0 enable
(ndfmcr0),20B0h ; WE enable, CLE enable
(ndfdtr0),00h ; Read command
(ndfmcr0),20D0h ; ALE enable
(ndfdtr0),xxh ; Address write (3 or 4 times)
1. Flag polling
2. Interrupt
(ndfmcr0),2015h ; Reset ECC, ECCE enable, CE0 enable
xx,(ndfdtr0) ; Data read (512 times)
(ndfmcr0),2010h ; ECC circuit disable
xx,(ndfdtr0) ; Redundancy data read (8 times)
xx,(ndfdtr0) ; ECC data read (3 times)
xx,(ndfdtr0) ; Redundancy data read (2 times)
xx,(ndfdtr0) ; ECC data read (3 times)
(ndfmcr0),2010h ; ECC circuit disable
xxxx,(ndeccrd0) ; Read ECC from internal circuit
1'st Read: D15-0 > LPR15:0
xxxx,(ndeccrd1) ; Read ECC from internal circuit
2'nd Read: D15-0 > FFh+CPR5:0+11b For first 256 bytes
xxxx,(ndeccrd0) ; Read ECC from internal circuit
3'rd Read: D15-0 > LPR15:0
xxxx,(ndeccrd1) ; Read ECC from internal circuit
4'th Read: D15-0 > FFh+CPR5:0+11b For second 256 bytes
92CZ26A-259
TMP92CZ26A
For first 256 bytes
For second 256 bytes