Toshiba H1 Series Data Book page 587

32bit micro controller tlcs-900/h1 series
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(2) Timing of INTRTC and Clock data
When time is read by interrupt, read clock data within 0.5s(s) after generating
interrupt. This is because count up of clock data occurs by rising edge of 1Hz pulse
cycle.
ALARM
INTRTC
1s counter
56
(Internal signal)
1s count UP
(Internal signal)
57
58
59
Figure 3.21.3 Timing of INTRTC and Clock data
92CZ26A-584
0
1
2
3
TMP92CZ26A
4

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