Toshiba H1 Series Data Book page 409

3.16.3.27 USBREADY Register
bit Symbol
USBREADY
(07E6H)
Read/Write
After reset
USBREADY (Bit0)
0: Writing to descriptor RAM was finished.
1: Writing to descriptor RAM is enable.
(However, when during connecting to host, writing to descriptor RAM is prohibited.)
VDD
INTXX
PortXX
(Pull-up on/off)
Write signal
case, UDC disable detecting USB_RESET signal until USBREADY register is written
"0" after released USB_RESET.
resister is connected to host in OFF condition, this condition is equivalent condition
with USB_RESET signal by pull-down resister in host side. Therefore UDC isn't
detected in USB_RESET until write "0" to USBREADY register
Note1: Pull-up resister and control switch are needed at external of TMP92CZ26A.
Note2: Above setting is example when communication. It is needed special circuit for prevent flow current at
connector connect detection , no-use, no connection.
This register informs finishing writing data to descriptor RAM on UDC.
After assigned data to descriptor RAM, write "0" to bit0.
7 6
USB host
GND
15 kΩ
15 kΩ
Detect level of VDD signal from USB cable, and execute initialize sequence. In this
If pull-up resister on D+ signal is controlled by using control signal, when pull-up
5 4
R1 = 1.5 kΩ
R2
R3
Descriptor RAM access
Device ID RAM
Register in USB
92CZ26A-406
TMP92CZ26A
3 2 1
TMP92CZ26A
VCC
VSS
CPU
PortXX
D+
UDC
D−
USBREADY registera access
0
USBREADY
R/W
0