Toshiba H1 Series Data Book page 507

The following shows how written data is output under various conditions.
When I2SnCTL<WLVLn> = 0
I2SnBUF register
Output order
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits 4'th Data
LSB-first 8 bits
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
When I2SnCTL<WLVLn> = 1
I2SnBUF register
Output order
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
3'rd Data
LSB-first 8 bits
MSB-first 16 bits
LSB-first 16 bits
MSB-first 8 bits
LSB-first 8 bits
Note: In case of using monaural setting, and change right / left: I2SnCTL<WLVLn>, data output order change
off 1'st data and 2'nd data.
31 30 29 28 27
2'nd Data
15 14 13 12 11
1'st Data
2'nd Data
31 30 29 28 27
1'st Data
15 14 13 12 11
2'nd Data
1'st Data
26 25 24 23
3'rd Data
4'th Data
10 9 8 7
1'st Data
2'nd Data
26 25 24 23
4'th Data
3'rd Data
10 9 8 7
2'nd Data
1'st Data
92CZ26A-504
TMP92CZ26A
22 21 20 19 18
6 5 4 3 2
22 21 20 19 18
6 5 4 3 2
17 16
2'nd Data
3'rd Data
1 0
1'st Data
1'st Data
17 16
1'st Data
4'th Data
1 0
2'nd Data
2'nd Data