Toshiba H1 Series Data Book page 356

(6) Transmitter/Receiver selection
Set the SBICR2<TRX> to "1" for operating the TMP92CZ26A as a transmitter.
Clear the <TRX> to "0" for operation as a receiver.
In Slave Mode,
Data with an addressing format is transferred
A slave address with the same value that an I2CAR
A GENERAL CALL is received (all 8-bit data are "0" after a start condition)
The <TRX> is set to "1" by the hardware if the direction bit (
master device is "1", and is cleared to "0" by the hardware if the bit is "0".
In the Master Mode, after an Acknowledge signal is returned from the slave device,
the <TRX> is cleared to "0" by the hardware if a transmitted direction bit is "1", and is
set to "1" by the hardware if it is "0". When an Acknowledge signal is not returned, the
current condition is maintained.
The <TRX> is cleared to "0" by the hardware after a stop condition on the I
detected or arbitration is lost.
(7) Start/Stop condition generation
When the SBISR<BB> is "0", slave address and direction bit which are set to
SBIDBR are output on a bus after generating a start condition by writing "1" to the
SBICR2 <MST, TRX, BB, PIN>. It is necessary to set transmitted data to the data
buffer register (SBIDBR) and set "1" to <ACK> beforehand.
SCL pin 1
SDA pin A6
Start condition
Figure 3.15.10 Start condition generation and slave address generation
When the <BB> is "1", a sequence of generating a stop condition is started by
writing "1" to the <MST, TRX, PIN>, and "0" to the <BB>. Do not modify the contents
of <MST, TRX, BB, PIN> until a stop condition is generated on a bus.
Figure 3.15.11 Stop condition generation
The state of the bus can be ascertained by reading the contents of SBISR<BB>.
SBISR<BB> will be set to 1 if a start condition has been detected on the bus, and will
be cleared to 0 if a stop condition has been detected.
2 3 4
A5 A4 A3
Slave address and the direction bit
SCL pin
SDA pin
Stop condition
92CZ26A-353
R/
5 6 7
A2 A1 A0
R/ W
TMP92CZ26A
W ) sent from the
C bus is
2
8 9
Acknowledge
signal